How to deal with substrate bounce in analog circuits in epi-type CMOS technology

Bram Nauta, Gian Hoogzaad, G. Hoogzaad

    Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

    Abstract

    Substrate noise is one of the key problems in mixed analog/digital ICs. Although measures are known to reduce substrate noise, the noise will never be completely eliminated since this requires larger chip area or exotic packages and thus higher cost. Analog circuits on digital ICs simply have to be resistant to substrate noise. A general strategy is given which can be summarized as: the supply of the analog circuits must be referred to the substrate and the analog signals must be referred to a clean analog ground. Furthermore several design constraints are given to minimize the effect of substrate noise on analog. Two bandgap circuits are discussed and it is shown that apparently minor design issues, such as the connection of an n-well of a PMOS differential pair, can have large impact on the substrate sensitivity of this circuit. This has been verified by measurements.
    Original languageUndefined
    Title of host publicationSubstrate Noise Coupling in Mixed Signal ASICs
    EditorsS. Donnay, G. Gielen
    PublisherKluwer Academic Publishers
    Pages257-270
    Number of pages13
    ISBN (Print)1-4020-7381-X
    DOIs
    Publication statusPublished - 2003

    Publication series

    Name
    PublisherKluwer Academic Publishers

    Keywords

    • IR-67647
    • EWI-14435
    • METIS-212939

    Cite this

    Nauta, B., Hoogzaad, G., & Hoogzaad, G. (2003). How to deal with substrate bounce in analog circuits in epi-type CMOS technology. In S. Donnay, & G. Gielen (Eds.), Substrate Noise Coupling in Mixed Signal ASICs (pp. 257-270). [10.1007/0-306-48170-7_12] Kluwer Academic Publishers. https://doi.org/10.1007/0-306-48170-7_12
    Nauta, Bram ; Hoogzaad, Gian ; Hoogzaad, G. / How to deal with substrate bounce in analog circuits in epi-type CMOS technology. Substrate Noise Coupling in Mixed Signal ASICs. editor / S. Donnay ; G. Gielen. Kluwer Academic Publishers, 2003. pp. 257-270
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    abstract = "Substrate noise is one of the key problems in mixed analog/digital ICs. Although measures are known to reduce substrate noise, the noise will never be completely eliminated since this requires larger chip area or exotic packages and thus higher cost. Analog circuits on digital ICs simply have to be resistant to substrate noise. A general strategy is given which can be summarized as: the supply of the analog circuits must be referred to the substrate and the analog signals must be referred to a clean analog ground. Furthermore several design constraints are given to minimize the effect of substrate noise on analog. Two bandgap circuits are discussed and it is shown that apparently minor design issues, such as the connection of an n-well of a PMOS differential pair, can have large impact on the substrate sensitivity of this circuit. This has been verified by measurements.",
    keywords = "IR-67647, EWI-14435, METIS-212939",
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    Nauta, B, Hoogzaad, G & Hoogzaad, G 2003, How to deal with substrate bounce in analog circuits in epi-type CMOS technology. in S Donnay & G Gielen (eds), Substrate Noise Coupling in Mixed Signal ASICs., 10.1007/0-306-48170-7_12, Kluwer Academic Publishers, pp. 257-270. https://doi.org/10.1007/0-306-48170-7_12

    How to deal with substrate bounce in analog circuits in epi-type CMOS technology. / Nauta, Bram; Hoogzaad, Gian; Hoogzaad, G.

    Substrate Noise Coupling in Mixed Signal ASICs. ed. / S. Donnay; G. Gielen. Kluwer Academic Publishers, 2003. p. 257-270 10.1007/0-306-48170-7_12.

    Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

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    Nauta B, Hoogzaad G, Hoogzaad G. How to deal with substrate bounce in analog circuits in epi-type CMOS technology. In Donnay S, Gielen G, editors, Substrate Noise Coupling in Mixed Signal ASICs. Kluwer Academic Publishers. 2003. p. 257-270. 10.1007/0-306-48170-7_12 https://doi.org/10.1007/0-306-48170-7_12