Hydra: an Energy-efficient and Reconfigurable Network Interface

M.D. van de Burgwal, Gerardus Johannes Maria Smit, G.K. Rauwerda, P.M. Heysters

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Abstract

    In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces the Hydra: a network interface for the Montium TP, a coarse-grained reconfigurable processor designed for DSP algorithms. We show that the Hydra is energy-efficient and provides the flexibility required to interface processing elements like the Montium TP.
    Original languageUndefined
    Title of host publicationProceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms
    Place of PublicationLas Vegas, USA
    PublisherCSREA Press
    Pages171-177
    Number of pages7
    ISBN (Print)1-60132-011-6
    Publication statusPublished - Jun 2006
    Event2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '06 - Las Vegas, United States
    Duration: 26 Jun 200629 Jun 2006

    Publication series

    Name
    PublisherCSREA Press
    Number2

    Conference

    Conference2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '06
    Abbreviated titleERSA
    CountryUnited States
    CityLas Vegas
    Period26/06/0629/06/06

    Keywords

    • EWI-2815
    • EC Grant Agreement nr.: FP6/001908
    • IR-62883
    • METIS-238028
    • CAES-EEA: Efficient Embedded Architectures

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