In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces the Hydra: a network interface for the Montium TP, a coarse-grained reconfigurable processor designed for DSP algorithms. We show that the Hydra is energy-efficient and provides the flexibility required to interface processing elements like the Montium TP.
|Conference||2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '06|
|Period||26/06/06 → 29/06/06|
- EC Grant Agreement nr.: FP6/001908
- CAES-EEA: Efficient Embedded Architectures