Abstract
In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.
Original language | Undefined |
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Title of host publication | Proceedings of the 44th European Solid State Device Research Conference, ESSDERC 2014 |
Place of Publication | USA |
Publisher | IEEE |
Pages | 321-324 |
Number of pages | 4 |
ISBN (Print) | 978-1-4799-4378-4 |
DOIs | |
Publication status | Published - 22 Sept 2014 |
Event | 44th European Solid State Device Research Conference, ESSDERC 2014 - Venice, Italy Duration: 22 Sept 2014 → 26 Sept 2014 Conference number: 44 |
Publication series
Name | |
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Publisher | IEEE Circuits & Systems Society |
ISSN (Print) | 1930-8876 |
Conference
Conference | 44th European Solid State Device Research Conference, ESSDERC 2014 |
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Abbreviated title | ESSDERC 2014 |
Country/Territory | Italy |
City | Venice |
Period | 22/09/14 → 26/09/14 |
Keywords
- stability factor
- IR-92858
- EWI-25334
- electrical runaway
- electro-thermal coupling
- parasitic bipolar
- failure function
- Power MOSFET
- impact ionization
- thermal runaway
- Safe Operating Area (SOA)
- Safe Operating Volume (SOV)
- Silicon-on-insulator (SOI)
- METIS-309675
- self-heating