Identifying failure mechanisms in LDMOS transistors by analytical stability analysis

A. Ferrara, P.G. Steeneken, B.K. Boksteen, A. Heringa, A.J. Scholten, Jurriaan Schmitz, Raymond Josephus Engelbart Hueting

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    1 Citation (Scopus)

    Abstract

    In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.
    Original languageUndefined
    Title of host publicationProceedings of the 44th European Solid State Device Research Conference, ESSDERC 2014
    Place of PublicationUSA
    PublisherIEEE Circuits & Systems Society
    Pages321-324
    Number of pages4
    ISBN (Print)978-1-4799-4378-4
    DOIs
    Publication statusPublished - 22 Sep 2014
    Event44th European Solid State Device Research Conference, ESSDERC 2014 - Venice, Italy
    Duration: 22 Sep 201426 Sep 2014
    Conference number: 44

    Publication series

    Name
    PublisherIEEE Circuits & Systems Society
    ISSN (Print)1930-8876

    Conference

    Conference44th European Solid State Device Research Conference, ESSDERC 2014
    Abbreviated titleESSDERC 2014
    CountryItaly
    CityVenice
    Period22/09/1426/09/14

    Keywords

    • stability factor
    • IR-92858
    • EWI-25334
    • electrical runaway
    • electro-thermal coupling
    • parasitic bipolar
    • failure function
    • Power MOSFET
    • impact ionization
    • thermal runaway
    • Safe Operating Area (SOA)
    • Safe Operating Volume (SOV)
    • Silicon-on-insulator (SOI)
    • METIS-309675
    • self-heating

    Cite this

    Ferrara, A., Steeneken, P. G., Boksteen, B. K., Heringa, A., Scholten, A. J., Schmitz, J., & Hueting, R. J. E. (2014). Identifying failure mechanisms in LDMOS transistors by analytical stability analysis. In Proceedings of the 44th European Solid State Device Research Conference, ESSDERC 2014 (pp. 321-324). USA: IEEE Circuits & Systems Society. https://doi.org/10.1109/ESSDERC.2014.6948825