Identifying failure mechanisms in LDMOS transistors by analytical stability analysis

A. Ferrara; P.G. Steeneken; B.K. Boksteen; A. Heringa; A.J. Scholten; Jurriaan Schmitz; Raymond Josephus Engelbart Hueting

doi:10.1109/ESSDERC.2014.6948825

Identifying failure mechanisms in LDMOS transistors by analytical stability analysis

A. Ferrara, P.G. Steeneken, B.K. Boksteen, A. Heringa, A.J. Scholten, Jurriaan Schmitz, Raymond Josephus Engelbart Hueting

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.

Original language	Undefined
Title of host publication	Proceedings of the 44th European Solid State Device Research Conference, ESSDERC 2014
Place of Publication	USA
Publisher	IEEE Circuits & Systems Society
Pages	321-324
Number of pages	4
ISBN (Print)	978-1-4799-4378-4
DOIs	https://doi.org/10.1109/ESSDERC.2014.6948825
Publication status	Published - 22 Sep 2014
Event	44th European Solid State Device Research Conference, ESSDERC 2014 - Venice, Italy Duration: 22 Sep 2014 → 26 Sep 2014 Conference number: 44

Publication series

Name
Publisher	IEEE Circuits & Systems Society
ISSN (Print)	1930-8876

Conference

Conference	44th European Solid State Device Research Conference, ESSDERC 2014
Abbreviated title	ESSDERC 2014
Country/Territory	Italy
City	Venice
Period	22/09/14 → 26/09/14

Keywords

stability factor
IR-92858
EWI-25334
electrical runaway
electro-thermal coupling
parasitic bipolar
failure function
Power MOSFET
impact ionization
thermal runaway
Safe Operating Area (SOA)
Safe Operating Volume (SOV)
Silicon-on-insulator (SOI)
METIS-309675
self-heating

Access to Document

10.1109/ESSDERC.2014.6948825

http://eprints.eemcs.utwente.nl/secure2/25334/01/D082-C7L-E1-9152_Essderc_Alessandro.pdf

Cite this

Ferrara, A., Steeneken, P. G., Boksteen, B. K., Heringa, A., Scholten, A. J., Schmitz, J., & Hueting, R. J. E. (2014). Identifying failure mechanisms in LDMOS transistors by analytical stability analysis. In Proceedings of the 44th European Solid State Device Research Conference, ESSDERC 2014 (pp. 321-324). IEEE Circuits & Systems Society. https://doi.org/10.1109/ESSDERC.2014.6948825

Ferrara, A. ; Steeneken, P.G. ; Boksteen, B.K. ; Heringa, A. ; Scholten, A.J. ; Schmitz, Jurriaan ; Hueting, Raymond Josephus Engelbart. / Identifying failure mechanisms in LDMOS transistors by analytical stability analysis. Proceedings of the 44th European Solid State Device Research Conference, ESSDERC 2014. USA : IEEE Circuits & Systems Society, 2014. pp. 321-324

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title = "Identifying failure mechanisms in LDMOS transistors by analytical stability analysis",

abstract = "In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.",

keywords = "stability factor, IR-92858, EWI-25334, electrical runaway, electro-thermal coupling, parasitic bipolar, failure function, Power MOSFET, impact ionization, thermal runaway, Safe Operating Area (SOA), Safe Operating Volume (SOV), Silicon-on-insulator (SOI), METIS-309675, self-heating",

author = "A. Ferrara and P.G. Steeneken and B.K. Boksteen and A. Heringa and A.J. Scholten and Jurriaan Schmitz and Hueting, {Raymond Josephus Engelbart}",

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doi = "10.1109/ESSDERC.2014.6948825",

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Ferrara, A, Steeneken, PG, Boksteen, BK, Heringa, A, Scholten, AJ, Schmitz, J & Hueting, RJE 2014, Identifying failure mechanisms in LDMOS transistors by analytical stability analysis. in Proceedings of the 44th European Solid State Device Research Conference, ESSDERC 2014. IEEE Circuits & Systems Society, USA, pp. 321-324, 44th European Solid State Device Research Conference, ESSDERC 2014, Venice, Italy, 22/09/14. https://doi.org/10.1109/ESSDERC.2014.6948825

Identifying failure mechanisms in LDMOS transistors by analytical stability analysis. / Ferrara, A.; Steeneken, P.G.; Boksteen, B.K.; Heringa, A.; Scholten, A.J.; Schmitz, Jurriaan ; Hueting, Raymond Josephus Engelbart.

Proceedings of the 44th European Solid State Device Research Conference, ESSDERC 2014. USA : IEEE Circuits & Systems Society, 2014. p. 321-324.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Identifying failure mechanisms in LDMOS transistors by analytical stability analysis

AU - Ferrara, A.

AU - Steeneken, P.G.

AU - Boksteen, B.K.

AU - Heringa, A.

AU - Scholten, A.J.

AU - Schmitz, Jurriaan

AU - Hueting, Raymond Josephus Engelbart

N1 - Conference code: 44

PY - 2014/9/22

Y1 - 2014/9/22

N2 - In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.

AB - In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors.

KW - stability factor

KW - IR-92858

KW - EWI-25334

KW - electrical runaway

KW - electro-thermal coupling

KW - parasitic bipolar

KW - failure function

KW - Power MOSFET

KW - impact ionization

KW - thermal runaway

KW - Safe Operating Area (SOA)

KW - Safe Operating Volume (SOV)

KW - Silicon-on-insulator (SOI)

KW - METIS-309675

KW - self-heating

U2 - 10.1109/ESSDERC.2014.6948825

DO - 10.1109/ESSDERC.2014.6948825

M3 - Conference contribution

SN - 978-1-4799-4378-4

SP - 321

EP - 324

BT - Proceedings of the 44th European Solid State Device Research Conference, ESSDERC 2014

PB - IEEE Circuits & Systems Society

CY - USA

Y2 - 22 September 2014 through 26 September 2014

ER -