Identifying FPGA IP-cores based on lookup table content analysis

Daniel Ziener*, Stefan Aßmus, Jürgen Teich

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

26 Citations (Scopus)

Abstract

In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP protection against unlicensed usage. We show methods to extract the content of the lookup tables in a design from a binary bitfile of Xilinx Virtex-II and Virtex-II Pro FPGAs. To identify a core, we compare the number of unique functions from lookup tables of the core with the lookup tables extracted from a product with an FPGA from an accused company. Also placement information can be used for increasing the reliability of the result. With these methods, no additional sources or information must be inquired from the accused company. These techniques can be used for netlist and bitfile cores, so a wide spectrum of cores can be identified.

Original languageEnglish
Title of host publication2006 International Conference on Field Programmable Logic and Applications, FPL
Pages481-486
Number of pages6
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event16th International Conference on Field Programmable Logic and Applications 2006 - Madrid, Spain
Duration: 28 Aug 200630 Aug 2006
Conference number: 16

Conference

Conference16th International Conference on Field Programmable Logic and Applications 2006
Abbreviated titleFPL 2006
CountrySpain
CityMadrid
Period28/08/0630/08/06

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