IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time

Ghazanfar Ali, Jerrin Pathrose Vareed, Hans G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    5 Citations (Scopus)
    2 Downloads (Pure)


    The monitoring of critical-paths in Systems-on-Chip to ensure dependable operation during the lifetime is becoming essential for safety-critical applications. Based on the timing information, different procedures like remaining lifetime prediction, voltage, and frequency scaling can be carried out to retain the desired functionality. To perform these operations, it is important to measure the run-time changing parameters like operating voltage and temperature, at the same moment of measuring slack-delay timing in critical paths. This will provide a better correlation, as compared to measuring the slack-delay timing alone, for instance, to determine the remaining lifetime. This paper presents a novel delay-line based voltage embedded instrument with a conversion time of just one clock cycle along with its integration to the IJTAG network. The proposed embedded instrument (EI) has been designed using the TSMC 40nm standard cell library. Simulation results of the proposed EI show a resolution of 10mV with a detection range from 0.95V to 1.20V, which is sufficient for most dependability applications.
    Original languageEnglish
    Title of host publication2019 IEEE Latin American Test Symposium (LATS)
    Number of pages6
    ISBN (Electronic)978-1-7281-1756-0
    Publication statusPublished - 6 May 2019
    Event20th IEEE Latin American Test Symposium 2019 - Santiago, Chile
    Duration: 11 Mar 201913 Mar 2019
    Conference number: 20


    Conference20th IEEE Latin American Test Symposium 2019
    Abbreviated titleLATS 2019
    Internet address


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