IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time

Ghazanfar Ali, Jerrin Pathrose Vareed, Hans G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    1 Citation (Scopus)
    1 Downloads (Pure)

    Abstract

    The monitoring of critical-paths in Systems-on-Chip to ensure dependable operation during the lifetime is becoming essential for safety-critical applications. Based on the timing information, different procedures like remaining lifetime prediction, voltage, and frequency scaling can be carried out to retain the desired functionality. To perform these operations, it is important to measure the run-time changing parameters like operating voltage and temperature, at the same moment of measuring slack-delay timing in critical paths. This will provide a better correlation, as compared to measuring the slack-delay timing alone, for instance, to determine the remaining lifetime. This paper presents a novel delay-line based voltage embedded instrument with a conversion time of just one clock cycle along with its integration to the IJTAG network. The proposed embedded instrument (EI) has been designed using the TSMC 40nm standard cell library. Simulation results of the proposed EI show a resolution of 10mV with a detection range from 0.95V to 1.20V, which is sufficient for most dependability applications.
    Original languageEnglish
    Title of host publication2019 IEEE Latin American Test Symposium (LATS)
    Number of pages6
    ISBN (Electronic)978-1-7281-1756-0
    DOIs
    Publication statusPublished - 6 May 2019
    Event20th IEEE Latin American Test Symposium 2019 - Santiago, Chile
    Duration: 11 Mar 201913 Mar 2019
    Conference number: 20
    http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/

    Conference

    Conference20th IEEE Latin American Test Symposium 2019
    Abbreviated titleLATS 2019
    CountryChile
    CitySantiago
    Period11/03/1913/03/19
    Internet address

    Fingerprint

    Electric delay lines
    Clocks
    Electric potential
    Monitoring
    Temperature

    Cite this

    @inproceedings{249f80ed21b44c5d83d8b910e317f686,
    title = "IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time",
    abstract = "The monitoring of critical-paths in Systems-on-Chip to ensure dependable operation during the lifetime is becoming essential for safety-critical applications. Based on the timing information, different procedures like remaining lifetime prediction, voltage, and frequency scaling can be carried out to retain the desired functionality. To perform these operations, it is important to measure the run-time changing parameters like operating voltage and temperature, at the same moment of measuring slack-delay timing in critical paths. This will provide a better correlation, as compared to measuring the slack-delay timing alone, for instance, to determine the remaining lifetime. This paper presents a novel delay-line based voltage embedded instrument with a conversion time of just one clock cycle along with its integration to the IJTAG network. The proposed embedded instrument (EI) has been designed using the TSMC 40nm standard cell library. Simulation results of the proposed EI show a resolution of 10mV with a detection range from 0.95V to 1.20V, which is sufficient for most dependability applications.",
    author = "Ghazanfar Ali and {Pathrose Vareed}, Jerrin and Kerkhoff, {Hans G.}",
    year = "2019",
    month = "5",
    day = "6",
    doi = "10.1109/LATW.2019.8704570",
    language = "English",
    booktitle = "2019 IEEE Latin American Test Symposium (LATS)",

    }

    Ali, G, Pathrose Vareed, J & Kerkhoff, HG 2019, IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time. in 2019 IEEE Latin American Test Symposium (LATS). 20th IEEE Latin American Test Symposium 2019, Santiago, Chile, 11/03/19. https://doi.org/10.1109/LATW.2019.8704570

    IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time. / Ali, Ghazanfar ; Pathrose Vareed, Jerrin ; Kerkhoff, Hans G.

    2019 IEEE Latin American Test Symposium (LATS). 2019.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    TY - GEN

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    AU - Ali, Ghazanfar

    AU - Pathrose Vareed, Jerrin

    AU - Kerkhoff, Hans G.

    PY - 2019/5/6

    Y1 - 2019/5/6

    N2 - The monitoring of critical-paths in Systems-on-Chip to ensure dependable operation during the lifetime is becoming essential for safety-critical applications. Based on the timing information, different procedures like remaining lifetime prediction, voltage, and frequency scaling can be carried out to retain the desired functionality. To perform these operations, it is important to measure the run-time changing parameters like operating voltage and temperature, at the same moment of measuring slack-delay timing in critical paths. This will provide a better correlation, as compared to measuring the slack-delay timing alone, for instance, to determine the remaining lifetime. This paper presents a novel delay-line based voltage embedded instrument with a conversion time of just one clock cycle along with its integration to the IJTAG network. The proposed embedded instrument (EI) has been designed using the TSMC 40nm standard cell library. Simulation results of the proposed EI show a resolution of 10mV with a detection range from 0.95V to 1.20V, which is sufficient for most dependability applications.

    AB - The monitoring of critical-paths in Systems-on-Chip to ensure dependable operation during the lifetime is becoming essential for safety-critical applications. Based on the timing information, different procedures like remaining lifetime prediction, voltage, and frequency scaling can be carried out to retain the desired functionality. To perform these operations, it is important to measure the run-time changing parameters like operating voltage and temperature, at the same moment of measuring slack-delay timing in critical paths. This will provide a better correlation, as compared to measuring the slack-delay timing alone, for instance, to determine the remaining lifetime. This paper presents a novel delay-line based voltage embedded instrument with a conversion time of just one clock cycle along with its integration to the IJTAG network. The proposed embedded instrument (EI) has been designed using the TSMC 40nm standard cell library. Simulation results of the proposed EI show a resolution of 10mV with a detection range from 0.95V to 1.20V, which is sufficient for most dependability applications.

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