IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation

The deployment of embedded instruments (EI) for online monitoring of a cyber-physical system-on-chip (CPSoC) for safety-critical applications has started getting more attention in recent years. Among these different types of EIs, the timing embedded instruments (to observe timing violations) are widely adopted to ensure a dependable operation during its operational lifetime. However, infield temperature variations together with self-aging of the timing EI affects its output, making it less reliable. This paper presents an IJTAG compatible, in-situ slack-delay timing embedded instrument to monitor critical paths in a CPSoC. The main contribution of the proposed design is the infield, online calibration mechanism. It enables the EI to self-calibrate for relatively fast-changing environmental variations like temperature, as well as slow changing variations like aging. The design has been implemented using a TSMC 40nm LP standard cell library. Simulation results show an average resolution of 13ps with a monitoring window of 13ps–416ps, which is sufficient to monitor the CPSoC for small timing margins. To further demonstrate the IJTAG compatibility, an FPGA implementation of the proposed design is also presented.