IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Downloads (Pure)

Abstract

The deployment of embedded instruments (EI) for online monitoring of a cyber-physical system-on-chip (CPSoC) for safety-critical applications has started getting more attention in recent years. Among these different types of EIs, the timing embedded instruments (to observe timing violations) are widely adopted to ensure a dependable operation during its operational lifetime. However, infield temperature variations together with self-aging of the timing EI affects its output, making it less reliable. This paper presents an IJTAG compatible, in-situ slack-delay timing embedded instrument to monitor critical paths in a CPSoC. The main contribution of the proposed design is the infield, online calibration mechanism. It enables the EI to self-calibrate for relatively fast-changing environmental variations like temperature, as well as slow changing variations like aging. The design has been implemented using a TSMC 40nm LP standard cell library. Simulation results show an average resolution of 13ps with a monitoring window of 13ps–416ps, which is sufficient to monitor the CPSoC for small timing margins. To further demonstrate the IJTAG compatibility, an FPGA implementation of the proposed design is also presented.
Original languageEnglish
Title of host publicationProceedings - 2019 IEEE European Test Symposium, ETS 2019
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Electronic)978-1-7281-1173-5, 978-1-7281-1172-8
ISBN (Print)978-1-7281-1174-2
DOIs
Publication statusPublished - 8 Aug 2019
Event24th IEEE European Test Symposium, ETS 2019 - Kongresshaus, Baden Baden, Germany
Duration: 27 May 201931 May 2019
Conference number: 24
https://www.testgroup.polito.it/ets19/

Publication series

NameProceedings of the European Test Workshop (ETS)
Volume2019
ISSN (Print)1530-1877
ISSN (Electronic)1558-1780

Conference

Conference24th IEEE European Test Symposium, ETS 2019
Abbreviated titleETS
CountryGermany
CityBaden Baden
Period27/05/1931/05/19
Internet address

Fingerprint

Aging of materials
Calibration
Monitoring
Field programmable gate arrays (FPGA)
Temperature
Cyber Physical System
System-on-chip

Keywords

  • Dependability
  • Timing monitoring
  • Self-Awareness
  • IJTAG
  • Embedded Instrument
  • System Awareness
  • Prognostics
  • CPSoC

Cite this

Ali, G., Pathros, J., & Kerkhoff, H. G. (2019). IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation. In Proceedings - 2019 IEEE European Test Symposium, ETS 2019 (pp. 1-6). [8791539] (Proceedings of the European Test Workshop (ETS); Vol. 2019). IEEE. https://doi.org/10.1109/ETS.2019.8791539
Ali, Ghazanfar ; Pathros, Jerrin ; Kerkhoff, Hans G. / IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation. Proceedings - 2019 IEEE European Test Symposium, ETS 2019. IEEE, 2019. pp. 1-6 (Proceedings of the European Test Workshop (ETS)).
@inproceedings{2272a89859964aae8d01a35858009443,
title = "IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation",
abstract = "The deployment of embedded instruments (EI) for online monitoring of a cyber-physical system-on-chip (CPSoC) for safety-critical applications has started getting more attention in recent years. Among these different types of EIs, the timing embedded instruments (to observe timing violations) are widely adopted to ensure a dependable operation during its operational lifetime. However, infield temperature variations together with self-aging of the timing EI affects its output, making it less reliable. This paper presents an IJTAG compatible, in-situ slack-delay timing embedded instrument to monitor critical paths in a CPSoC. The main contribution of the proposed design is the infield, online calibration mechanism. It enables the EI to self-calibrate for relatively fast-changing environmental variations like temperature, as well as slow changing variations like aging. The design has been implemented using a TSMC 40nm LP standard cell library. Simulation results show an average resolution of 13ps with a monitoring window of 13ps–416ps, which is sufficient to monitor the CPSoC for small timing margins. To further demonstrate the IJTAG compatibility, an FPGA implementation of the proposed design is also presented.",
keywords = "Dependability, Timing monitoring, Self-Awareness, IJTAG, Embedded Instrument, System Awareness, Prognostics, CPSoC",
author = "Ghazanfar Ali and Jerrin Pathros and Kerkhoff, {Hans G.}",
year = "2019",
month = "8",
day = "8",
doi = "10.1109/ETS.2019.8791539",
language = "English",
isbn = "978-1-7281-1174-2",
series = "Proceedings of the European Test Workshop (ETS)",
publisher = "IEEE",
pages = "1--6",
booktitle = "Proceedings - 2019 IEEE European Test Symposium, ETS 2019",
address = "United States",

}

Ali, G, Pathros, J & Kerkhoff, HG 2019, IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation. in Proceedings - 2019 IEEE European Test Symposium, ETS 2019., 8791539, Proceedings of the European Test Workshop (ETS), vol. 2019, IEEE, pp. 1-6, 24th IEEE European Test Symposium, ETS 2019, Baden Baden, Germany, 27/05/19. https://doi.org/10.1109/ETS.2019.8791539

IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation. / Ali, Ghazanfar ; Pathros, Jerrin ; Kerkhoff, Hans G.

Proceedings - 2019 IEEE European Test Symposium, ETS 2019. IEEE, 2019. p. 1-6 8791539 (Proceedings of the European Test Workshop (ETS); Vol. 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation

AU - Ali, Ghazanfar

AU - Pathros, Jerrin

AU - Kerkhoff, Hans G.

PY - 2019/8/8

Y1 - 2019/8/8

N2 - The deployment of embedded instruments (EI) for online monitoring of a cyber-physical system-on-chip (CPSoC) for safety-critical applications has started getting more attention in recent years. Among these different types of EIs, the timing embedded instruments (to observe timing violations) are widely adopted to ensure a dependable operation during its operational lifetime. However, infield temperature variations together with self-aging of the timing EI affects its output, making it less reliable. This paper presents an IJTAG compatible, in-situ slack-delay timing embedded instrument to monitor critical paths in a CPSoC. The main contribution of the proposed design is the infield, online calibration mechanism. It enables the EI to self-calibrate for relatively fast-changing environmental variations like temperature, as well as slow changing variations like aging. The design has been implemented using a TSMC 40nm LP standard cell library. Simulation results show an average resolution of 13ps with a monitoring window of 13ps–416ps, which is sufficient to monitor the CPSoC for small timing margins. To further demonstrate the IJTAG compatibility, an FPGA implementation of the proposed design is also presented.

AB - The deployment of embedded instruments (EI) for online monitoring of a cyber-physical system-on-chip (CPSoC) for safety-critical applications has started getting more attention in recent years. Among these different types of EIs, the timing embedded instruments (to observe timing violations) are widely adopted to ensure a dependable operation during its operational lifetime. However, infield temperature variations together with self-aging of the timing EI affects its output, making it less reliable. This paper presents an IJTAG compatible, in-situ slack-delay timing embedded instrument to monitor critical paths in a CPSoC. The main contribution of the proposed design is the infield, online calibration mechanism. It enables the EI to self-calibrate for relatively fast-changing environmental variations like temperature, as well as slow changing variations like aging. The design has been implemented using a TSMC 40nm LP standard cell library. Simulation results show an average resolution of 13ps with a monitoring window of 13ps–416ps, which is sufficient to monitor the CPSoC for small timing margins. To further demonstrate the IJTAG compatibility, an FPGA implementation of the proposed design is also presented.

KW - Dependability

KW - Timing monitoring

KW - Self-Awareness

KW - IJTAG

KW - Embedded Instrument

KW - System Awareness

KW - Prognostics

KW - CPSoC

UR - http://www.scopus.com/inward/record.url?scp=85071196457&partnerID=8YFLogxK

U2 - 10.1109/ETS.2019.8791539

DO - 10.1109/ETS.2019.8791539

M3 - Conference contribution

SN - 978-1-7281-1174-2

T3 - Proceedings of the European Test Workshop (ETS)

SP - 1

EP - 6

BT - Proceedings - 2019 IEEE European Test Symposium, ETS 2019

PB - IEEE

ER -

Ali G, Pathros J, Kerkhoff HG. IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation. In Proceedings - 2019 IEEE European Test Symposium, ETS 2019. IEEE. 2019. p. 1-6. 8791539. (Proceedings of the European Test Workshop (ETS)). https://doi.org/10.1109/ETS.2019.8791539