In this paper we present a systematic study on the effect of process and layout variation for groundedgate NMOSTs and LVTSCRs in a 0.18m technology under negative non-socketed Charged Device Model (CDM) stress. A comparison of the CDM test results with those of ggNMOSTs in various other technologies is also presented. It is shown that the CDM robustness of ggNMOSTs increases with technology scaling and that the performance of LVTSCRs can be as good as that of ggNMOSTs under CDM stresses.
|Number of pages||4|
|Publication status||Published - 27 Nov 2002|
|Event||5th Annual Workshop on Semiconductors Advances for Future Electronics, SAFE 2002 - Veldhoven, Netherlands|
Duration: 27 Nov 2002 → 28 Nov 2002
Conference number: 5
|Workshop||5th Annual Workshop on Semiconductors Advances for Future Electronics, SAFE 2002|
|Period||27/11/02 → 28/11/02|
- non-socketed CDM stress
Sowariraj, M. S. B., Kuper, F. G., Salm, C., Mouthaan, A. J., & Smedes, T. (2002). Impact of layout and technology variation on the CDM performance of ggNMOSTs and SCRs. 104-107. Paper presented at 5th Annual Workshop on Semiconductors Advances for Future Electronics, SAFE 2002, Veldhoven, Netherlands.