Impact of layout and technology variation on the CDM performance of ggNMOSTs and SCRs

M.S.B. Sowariraj, F.G. Kuper, Cora Salm, A.J. Mouthaan, T Smedes

    Research output: Contribution to conference › Paper

    Abstract

    In this paper we present a systematic study on the effect of process and layout variation for groundedgate NMOSTs and LVTSCRs in a 0.18m technology under negative non-socketed Charged Device Model (CDM) stress. A comparison of the CDM test results with those of ggNMOSTs in various other technologies is also presented. It is shown that the CDM robustness of ggNMOSTs increases with technology scaling and that the performance of LVTSCRs can be as good as that of ggNMOSTs under CDM stresses.
    Original languageUndefined
    Pages104-107
    Number of pages4
    Publication statusPublished - 27 Nov 2002
    Event5th Annual Workshop on Semiconductors Advances for Future Electronics, SAFE 2002 - Veldhoven, Netherlands
    Duration: 27 Nov 2002 → 28 Nov 2002
    Conference number: 5

    Workshop

    Workshop5th Annual Workshop on Semiconductors Advances for Future Electronics, SAFE 2002
    Abbreviated titleSAFE
    CountryNetherlands
    CityVeldhoven
    Period27/11/02 → 28/11/02

    Keywords

    • CDM
    • non-socketed CDM stress
    • IR-67768
    • EWI-15600
    • LVTSCR

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    Cite this

    Sowariraj, M. S. B., Kuper, F. G., Salm, C., Mouthaan, A. J., & Smedes, T. (2002). Impact of layout and technology variation on the CDM performance of ggNMOSTs and SCRs. 104-107. Paper presented at 5th Annual Workshop on Semiconductors Advances for Future Electronics, SAFE 2002, Veldhoven, Netherlands.