Impact of source/drain implants on threshold voltage matching in deep sub-micron CMOS technologies

Jerôme Dubois*, Johan Knol, Mike Bolt, Hans Tuinhout, Jurriaan Schmitz, Peter Stolk

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

13 Citations (Scopus)
4 Downloads (Pure)

Abstract

A new mechanism causing deterioration of the threshold voltage matching performance of MOSFETs is described. We demonstrate that this effect depends on several fundamental CMOS device architecture aspects such as the source/drain implant energies, the gate layer thickness, a gate top oxide layer thickness and the polysilicon gate morphology. It is concluded that penetration of a small (fluctuating) fraction of the LDD and HDD source drain implants through the gate can be responsible for severe degeneration of the matching performance of deep sub-micron CMOS technologies.

Original languageEnglish
Title of host publicationESSDERC 2002
Subtitle of host publicationProceedings of the 32nd European Solid-State Device Research Conference, Firenze, Italy, 24-26 September 2002
EditorsElena Gnani, Giorgio Baccarani, Massimo Rudan
Place of PublicationPiscataway, NJ
PublisherIEEE Computer Society
Pages115-118
Number of pages4
ISBN (Print)88-900847-8-2
DOIs
Publication statusPublished - 1 Jan 2002
Externally publishedYes
Event32nd European Solid-State Device Research Conference, ESSDERC 2002 - Firenze, Italy
Duration: 24 Sep 200226 Sep 2002
Conference number: 32

Conference

Conference32nd European Solid-State Device Research Conference, ESSDERC 2002
Abbreviated titleESSDERC
CountryItaly
CityFirenze
Period24/09/0226/09/02

Keywords

  • CMOS technology
  • Circuits
  • Fasteners
  • Morphology
  • MOS devices
  • CMOS process
  • MOSFETs
  • Fluctuations
  • Threshold voltage
  • Implants

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  • Cite this

    Dubois, J., Knol, J., Bolt, M., Tuinhout, H., Schmitz, J., & Stolk, P. (2002). Impact of source/drain implants on threshold voltage matching in deep sub-micron CMOS technologies. In E. Gnani, G. Baccarani, & M. Rudan (Eds.), ESSDERC 2002: Proceedings of the 32nd European Solid-State Device Research Conference, Firenze, Italy, 24-26 September 2002 (pp. 115-118). Piscataway, NJ: IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2002.194883