Abstract
A new mechanism causing deterioration of the threshold voltage matching performance of MOSFETs is described. We demonstrate that this effect depends on several fundamental CMOS device architecture aspects such as the source/drain implant energies, the gate layer thickness, a gate top oxide layer thickness and the polysilicon gate morphology. It is concluded that penetration of a small (fluctuating) fraction of the LDD and HDD source drain implants through the gate can be responsible for severe degeneration of the matching performance of deep sub-micron CMOS technologies.
| Original language | English |
|---|---|
| Title of host publication | ESSDERC 2002 |
| Subtitle of host publication | Proceedings of the 32nd European Solid-State Device Research Conference, Firenze, Italy, 24-26 September 2002 |
| Editors | Elena Gnani, Giorgio Baccarani, Massimo Rudan |
| Place of Publication | Piscataway, NJ |
| Publisher | IEEE |
| Pages | 115-118 |
| Number of pages | 4 |
| ISBN (Print) | 88-900847-8-2 |
| DOIs | |
| Publication status | Published - 1 Jan 2002 |
| Externally published | Yes |
| Event | 32nd European Solid-State Device Research Conference, ESSDERC 2002 - Firenze, Italy Duration: 24 Sept 2002 → 26 Sept 2002 Conference number: 32 |
Conference
| Conference | 32nd European Solid-State Device Research Conference, ESSDERC 2002 |
|---|---|
| Abbreviated title | ESSDERC |
| Country/Territory | Italy |
| City | Firenze |
| Period | 24/09/02 → 26/09/02 |
Keywords
- CMOS technology
- Circuits
- Fasteners
- Morphology
- MOS devices
- CMOS process
- MOSFETs
- Fluctuations
- Threshold voltage
- Implants
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