Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

L.T. Smit; G.K. Rauwerda; Albert Molderink; P.T. Wolkotte; Gerardus Johannes Maria Smit

doi:10.1109/FPL.2007.4380717

Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

L.T. Smit, G.K. Rauwerda, Albert Molderink, P.T. Wolkotte, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

10 Citations (Scopus)

208 Downloads (Pure)

Abstract

This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.

Original language	Undefined
Title of host publication	Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007
Place of Publication	Los Alamitos
Publisher	IEEE
Pages	562-566
Number of pages	5
ISBN (Print)	1-4244-1060-6
DOIs	https://doi.org/10.1109/FPL.2007.4380717
Publication status	Published - Aug 2007
Event	17th International Conference on Field Programmable Logic and Applications, FPL 2007 - Movenpick Hotel, Amsterdam, Netherlands Duration: 27 Aug 2007 → 29 Aug 2007 Conference number: 17

Publication series

Name
Publisher	IEEE Computer Society Press
Number	LNCS4549

Conference

Conference	17th International Conference on Field Programmable Logic and Applications, FPL 2007
Abbreviated title	FPL
Country/Territory	Netherlands
City	Amsterdam
Period	27/08/07 → 29/08/07

Keywords

CAES-EEA: Efficient Embedded Architectures
EWI-10992
IR-64324
METIS-242195
EC Grant Agreement nr.: FP6/001908

Access to Document

10.1109/FPL.2007.4380717

Cite this

@inproceedings{4545e8ff6bf947fab98f4b4aa5b6707c,

title = "Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core",

abstract = "This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.",

keywords = "CAES-EEA: Efficient Embedded Architectures, EWI-10992, IR-64324, METIS-242195, EC Grant Agreement nr.: FP6/001908",

author = "L.T. Smit and G.K. Rauwerda and Albert Molderink and P.T. Wolkotte and Smit, {Gerardus Johannes Maria}",

year = "2007",

month = aug,

doi = "10.1109/FPL.2007.4380717",

language = "Undefined",

isbn = "1-4244-1060-6",

publisher = "IEEE",

number = "LNCS4549",

pages = "562--566",

booktitle = "Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007",

address = "United States",

note = "17th International Conference on Field Programmable Logic and Applications, FPL 2007 ; Conference date: 27-08-2007 Through 29-08-2007",

}

Smit, LT, Rauwerda, GK, Molderink, A, Wolkotte, PT & Smit, GJM 2007, Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. in Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007. IEEE, Los Alamitos, pp. 562-566, 17th International Conference on Field Programmable Logic and Applications, FPL 2007, Amsterdam, Netherlands, 27/08/07. https://doi.org/10.1109/FPL.2007.4380717

Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. / Smit, L.T.; Rauwerda, G.K.; Molderink, Albert et al.
Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007. Los Alamitos: IEEE, 2007. p. 562-566.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

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AU - Rauwerda, G.K.

AU - Molderink, Albert

AU - Wolkotte, P.T.

AU - Smit, Gerardus Johannes Maria

N1 - Conference code: 17

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N2 - This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.

AB - This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.

KW - CAES-EEA: Efficient Embedded Architectures

KW - EWI-10992

KW - IR-64324

KW - METIS-242195

KW - EC Grant Agreement nr.: FP6/001908

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DO - 10.1109/FPL.2007.4380717

M3 - Conference contribution

SN - 1-4244-1060-6

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BT - Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007

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CY - Los Alamitos

T2 - 17th International Conference on Field Programmable Logic and Applications, FPL 2007

Y2 - 27 August 2007 through 29 August 2007

ER -