Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

L.T. Smit, G.K. Rauwerda, Albert Molderink, P.T. Wolkotte, Gerardus Johannes Maria Smit

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    10 Citations (Scopus)
    70 Downloads (Pure)

    Abstract

    This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.
    Original languageUndefined
    Title of host publicationProceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007
    Place of PublicationLos Alamitos
    PublisherIEEE Computer Society Press
    Pages562-566
    Number of pages5
    ISBN (Print)1-4244-1060-6
    DOIs
    Publication statusPublished - Aug 2007
    Event17th International Conference on Field Programmable Logic and Applications, FPL 2007 - Movenpick Hotel, Amsterdam, Netherlands
    Duration: 27 Aug 200729 Aug 2007
    Conference number: 17

    Publication series

    Name
    PublisherIEEE Computer Society Press
    NumberLNCS4549

    Conference

    Conference17th International Conference on Field Programmable Logic and Applications, FPL 2007
    Abbreviated titleFPL
    CountryNetherlands
    CityAmsterdam
    Period27/08/0729/08/07

    Keywords

    • CAES-EEA: Efficient Embedded Architectures
    • EWI-10992
    • IR-64324
    • METIS-242195
    • EC Grant Agreement nr.: FP6/001908

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