Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

L.T. Smit, G.K. Rauwerda, Albert Molderink, P.T. Wolkotte, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

10 Citations (Scopus)
54 Downloads (Pure)

Abstract

This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.
Original languageUndefined
Title of host publicationProceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007
Place of PublicationLos Alamitos
PublisherIEEE Computer Society Press
Pages562-566
Number of pages5
ISBN (Print)1-4244-1060-6
DOIs
Publication statusPublished - Aug 2007
Event17th International Conference on Field Programmable Logic and Applications, FPL 2007 - Movenpick Hotel, Amsterdam, Netherlands
Duration: 27 Aug 200729 Aug 2007
Conference number: 17

Publication series

Name
PublisherIEEE Computer Society Press
NumberLNCS4549

Conference

Conference17th International Conference on Field Programmable Logic and Applications, FPL 2007
Abbreviated titleFPL
CountryNetherlands
CityAmsterdam
Period27/08/0729/08/07

Keywords

  • CAES-EEA: Efficient Embedded Architectures
  • EWI-10992
  • IR-64324
  • METIS-242195
  • EC Grant Agreement nr.: FP6/001908

Cite this

Smit, L. T., Rauwerda, G. K., Molderink, A., Wolkotte, P. T., & Smit, G. J. M. (2007). Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. In Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007 (pp. 562-566). Los Alamitos: IEEE Computer Society Press. https://doi.org/10.1109/FPL.2007.4380717
Smit, L.T. ; Rauwerda, G.K. ; Molderink, Albert ; Wolkotte, P.T. ; Smit, Gerardus Johannes Maria. / Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007. Los Alamitos : IEEE Computer Society Press, 2007. pp. 562-566
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abstract = "This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.",
keywords = "CAES-EEA: Efficient Embedded Architectures, EWI-10992, IR-64324, METIS-242195, EC Grant Agreement nr.: FP6/001908",
author = "L.T. Smit and G.K. Rauwerda and Albert Molderink and P.T. Wolkotte and Smit, {Gerardus Johannes Maria}",
year = "2007",
month = "8",
doi = "10.1109/FPL.2007.4380717",
language = "Undefined",
isbn = "1-4244-1060-6",
publisher = "IEEE Computer Society Press",
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Smit, LT, Rauwerda, GK, Molderink, A, Wolkotte, PT & Smit, GJM 2007, Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. in Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007. IEEE Computer Society Press, Los Alamitos, pp. 562-566, 17th International Conference on Field Programmable Logic and Applications, FPL 2007, Amsterdam, Netherlands, 27/08/07. https://doi.org/10.1109/FPL.2007.4380717

Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. / Smit, L.T.; Rauwerda, G.K.; Molderink, Albert; Wolkotte, P.T.; Smit, Gerardus Johannes Maria.

Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007. Los Alamitos : IEEE Computer Society Press, 2007. p. 562-566.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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T1 - Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

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AU - Smit, Gerardus Johannes Maria

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AB - This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.

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KW - IR-64324

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KW - EC Grant Agreement nr.: FP6/001908

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Smit LT, Rauwerda GK, Molderink A, Wolkotte PT, Smit GJM. Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. In Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007. Los Alamitos: IEEE Computer Society Press. 2007. p. 562-566 https://doi.org/10.1109/FPL.2007.4380717