Abstract
This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.
Original language | Undefined |
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Title of host publication | Proceedings of the 2007 International Conference on Field Programmable Logic and Applications, FPL 2007 |
Place of Publication | Los Alamitos |
Publisher | IEEE |
Pages | 562-566 |
Number of pages | 5 |
ISBN (Print) | 1-4244-1060-6 |
DOIs | |
Publication status | Published - Aug 2007 |
Event | 17th International Conference on Field Programmable Logic and Applications, FPL 2007 - Movenpick Hotel, Amsterdam, Netherlands Duration: 27 Aug 2007 → 29 Aug 2007 Conference number: 17 |
Publication series
Name | |
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Publisher | IEEE Computer Society Press |
Number | LNCS4549 |
Conference
Conference | 17th International Conference on Field Programmable Logic and Applications, FPL 2007 |
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Abbreviated title | FPL |
Country/Territory | Netherlands |
City | Amsterdam |
Period | 27/08/07 → 29/08/07 |
Keywords
- CAES-EEA: Efficient Embedded Architectures
- EWI-10992
- IR-64324
- METIS-242195
- EC Grant Agreement nr.: FP6/001908