Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture

P.M. Heysters, G.K. Rauwerda, Gerardus Johannes Maria Smit

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    5 Citations (Scopus)
    183 Downloads (Pure)


    Summary form only given. A heterogeneous system-on-chip (SoC) architecture for mobile hand-held devices is proposed to overcome the battery bottleneck in these devices. This SoC contains processing tiles of different granularities. The Montium coarse-grain reconfigurable tile processor is presented. Also, an introduction to HiperLAN/2 baseband processing is given. The implementation of a HiperLAN/2 receiver on the Montium reconfigurable architecture is explained in detail. The hardware of this implemented receiver has been simulated and the performance figures are given. The configuration overhead for the receiver is very small, which enables dynamic reconfiguration. The required computational performance can be obtained at very low clock frequencies. The Montium coarse-grain reconfigurable architecture enables an energy and area efficient implementation of a HiperLAN/2 receiver.
    Original languageEnglish
    Title of host publicationProceedings of the 18th International Parallel & Distributed Processing Symposium (IPDPS 2004)
    Place of PublicationSanta Fe, New Mexico
    Number of pages8
    ISBN (Print)0-7695-2132-0
    Publication statusPublished - Apr 2004
    Event11th Reconfigurable Architectures Workshop, RAW 2004 - Eldorado Hotel, Santa Fé, United States
    Duration: 26 Apr 200427 Apr 2004
    Conference number: 11

    Publication series



    Conference11th Reconfigurable Architectures Workshop, RAW 2004
    Abbreviated titleRAW
    Country/TerritoryUnited States
    CitySanta Fé
    Internet address


    • CAES-EEA: Efficient Embedded Architectures
    • IR-48852
    • METIS-220626
    • EWI-1503


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