Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture

P.M. Heysters; G.K. Rauwerda; Gerardus Johannes Maria Smit

doi:10.1109/IPDPS.2004.1303131

Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture

P.M. Heysters, G.K. Rauwerda, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

219 Downloads (Pure)

Abstract

Summary form only given. A heterogeneous system-on-chip (SoC) architecture for mobile hand-held devices is proposed to overcome the battery bottleneck in these devices. This SoC contains processing tiles of different granularities. The Montium coarse-grain reconfigurable tile processor is presented. Also, an introduction to HiperLAN/2 baseband processing is given. The implementation of a HiperLAN/2 receiver on the Montium reconfigurable architecture is explained in detail. The hardware of this implemented receiver has been simulated and the performance figures are given. The configuration overhead for the receiver is very small, which enables dynamic reconfiguration. The required computational performance can be obtained at very low clock frequencies. The Montium coarse-grain reconfigurable architecture enables an energy and area efficient implementation of a HiperLAN/2 receiver.

Original language	English
Title of host publication	Proceedings of the 18th International Parallel & Distributed Processing Symposium (IPDPS 2004)
Place of Publication	Santa Fe, New Mexico
Publisher	IEEE
Pages	10
Number of pages	8
ISBN (Print)	0-7695-2132-0
DOIs	https://doi.org/10.1109/IPDPS.2004.1303131
Publication status	Published - Apr 2004
Event	11th Reconfigurable Architectures Workshop, RAW 2004 - Eldorado Hotel, Santa Fé, United States Duration: 26 Apr 2004 → 27 Apr 2004 Conference number: 11 http://www.ece.lsu.edu/vaidy/raw04/cfp.html

Publication series

Name
Publisher	IEEE

Conference

Conference	11th Reconfigurable Architectures Workshop, RAW 2004
Abbreviated title	RAW
Country/Territory	United States
City	Santa Fé
Period	26/04/04 → 27/04/04
Internet address	http://www.ece.lsu.edu/vaidy/raw04/cfp.html

Keywords

CAES-EEA: Efficient Embedded Architectures
IR-48852
METIS-220626
EWI-1503

Access to Document

10.1109/IPDPS.2004.1303131

heysters_raw04

http://doi.ieeecomputersociety.org/10.1109/IPDPS.2004.1303131

Cite this

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title = "Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture",

abstract = "Summary form only given. A heterogeneous system-on-chip (SoC) architecture for mobile hand-held devices is proposed to overcome the battery bottleneck in these devices. This SoC contains processing tiles of different granularities. The Montium coarse-grain reconfigurable tile processor is presented. Also, an introduction to HiperLAN/2 baseband processing is given. The implementation of a HiperLAN/2 receiver on the Montium reconfigurable architecture is explained in detail. The hardware of this implemented receiver has been simulated and the performance figures are given. The configuration overhead for the receiver is very small, which enables dynamic reconfiguration. The required computational performance can be obtained at very low clock frequencies. The Montium coarse-grain reconfigurable architecture enables an energy and area efficient implementation of a HiperLAN/2 receiver.",

keywords = "CAES-EEA: Efficient Embedded Architectures, IR-48852, METIS-220626, EWI-1503",

author = "P.M. Heysters and G.K. Rauwerda and Smit, {Gerardus Johannes Maria}",

note = "Imported from CHAMELEON.xml; 11th Reconfigurable Architectures Workshop, RAW 2004, RAW ; Conference date: 26-04-2004 Through 27-04-2004",

year = "2004",

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doi = "10.1109/IPDPS.2004.1303131",

language = "English",

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publisher = "IEEE",

pages = "10",

booktitle = "Proceedings of the 18th International Parallel & Distributed Processing Symposium (IPDPS 2004)",

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Heysters, PM, Rauwerda, GK & Smit, GJM 2004, Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture. in Proceedings of the 18th International Parallel & Distributed Processing Symposium (IPDPS 2004). IEEE, Santa Fe, New Mexico, pp. 10, 11th Reconfigurable Architectures Workshop, RAW 2004, Santa Fé, New Mexico, United States, 26/04/04. https://doi.org/10.1109/IPDPS.2004.1303131

Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture. / Heysters, P.M.; Rauwerda, G.K.; Smit, Gerardus Johannes Maria.
Proceedings of the 18th International Parallel & Distributed Processing Symposium (IPDPS 2004). Santa Fe, New Mexico: IEEE, 2004. p. 10.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - Summary form only given. A heterogeneous system-on-chip (SoC) architecture for mobile hand-held devices is proposed to overcome the battery bottleneck in these devices. This SoC contains processing tiles of different granularities. The Montium coarse-grain reconfigurable tile processor is presented. Also, an introduction to HiperLAN/2 baseband processing is given. The implementation of a HiperLAN/2 receiver on the Montium reconfigurable architecture is explained in detail. The hardware of this implemented receiver has been simulated and the performance figures are given. The configuration overhead for the receiver is very small, which enables dynamic reconfiguration. The required computational performance can be obtained at very low clock frequencies. The Montium coarse-grain reconfigurable architecture enables an energy and area efficient implementation of a HiperLAN/2 receiver.

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KW - EWI-1503

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Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture

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