Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures

Arnaud Rivaton, Jérôme Quevremont, Q. Zhang, P.T. Wolkotte, Gerardus Johannes Maria Smit

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    12 Citations (Scopus)
    92 Downloads (Pure)

    Abstract

    To improve power figures of a dual ARM9 RISC core architecture targeting low-power digital broadcasting applications, the addition of a coarse-grain architecture is considered. This paper introduces two of these structures: PACT's XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a Fast Fourier Transform on 1920 complex samples on both of them. Results in terms of processing time, resource utilization and energy dissipation are described and compared to those we have obtained on the RISC core. Then, as a conclusion, the paper presents the next steps of the development and some development issues.
    Original languageUndefined
    Title of host publicationProceedings of the International Symposium on System-on-Chip (SoC 2005)
    EditorsJ. Nurmi, J. Takala, T.D. Hamalainen
    Place of PublicationPiscataway, New Jersey, USA
    PublisherIEEE
    Pages82-85
    Number of pages4
    ISBN (Print)0-7803-9294-9
    DOIs
    Publication statusPublished - Nov 2005

    Publication series

    Name
    PublisherIEEE

    Keywords

    • EWI-1670
    • IR-54759
    • METIS-229225
    • CAES-EEA: Efficient Embedded Architectures

    Cite this

    Rivaton, A., Quevremont, J., Zhang, Q., Wolkotte, P. T., & Smit, G. J. M. (2005). Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures. In J. Nurmi, J. Takala, & T. D. Hamalainen (Eds.), Proceedings of the International Symposium on System-on-Chip (SoC 2005) (pp. 82-85). Piscataway, New Jersey, USA: IEEE. https://doi.org/10.1109/ISSOC.2005.1595648