To improve power figures of a dual ARM9 RISC core architecture targeting low-power digital broadcasting applications, the addition of a coarse-grain architecture is considered. This paper introduces two of these structures: PACT's XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a Fast Fourier Transform on 1920 complex samples on both of them. Results in terms of processing time, resource utilization and energy dissipation are described and compared to those we have obtained on the RISC core. Then, as a conclusion, the paper presents the next steps of the development and some development issues.
|Title of host publication||Proceedings of the International Symposium on System-on-Chip (SoC 2005)|
|Editors||J. Nurmi, J. Takala, T.D. Hamalainen|
|Place of Publication||Piscataway, New Jersey, USA|
|Number of pages||4|
|Publication status||Published - Nov 2005|
- CAES-EEA: Efficient Embedded Architectures
Rivaton, A., Quevremont, J., Zhang, Q., Wolkotte, P. T., & Smit, G. J. M. (2005). Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures. In J. Nurmi, J. Takala, & T. D. Hamalainen (Eds.), Proceedings of the International Symposium on System-on-Chip (SoC 2005) (pp. 82-85). Piscataway, New Jersey, USA: IEEE. https://doi.org/10.1109/ISSOC.2005.1595648