Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures

Arnaud Rivaton; Jérôme Quevremont; Q. Zhang; P.T. Wolkotte; Gerardus Johannes Maria Smit

doi:10.1109/ISSOC.2005.1595648

Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures

Arnaud Rivaton, Jérôme Quevremont, Q. Zhang, P.T. Wolkotte, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

14 Citations (Scopus)

337 Downloads (Pure)

Abstract

To improve power figures of a dual ARM9 RISC core architecture targeting low-power digital broadcasting applications, the addition of a coarse-grain architecture is considered. This paper introduces two of these structures: PACT's XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a Fast Fourier Transform on 1920 complex samples on both of them. Results in terms of processing time, resource utilization and energy dissipation are described and compared to those we have obtained on the RISC core. Then, as a conclusion, the paper presents the next steps of the development and some development issues.

Original language	Undefined
Title of host publication	Proceedings of the International Symposium on System-on-Chip (SoC 2005)
Editors	J. Nurmi, J. Takala, T.D. Hamalainen
Place of Publication	Piscataway, New Jersey, USA
Publisher	IEEE
Pages	82-85
Number of pages	4
ISBN (Print)	0-7803-9294-9
DOIs	https://doi.org/10.1109/ISSOC.2005.1595648
Publication status	Published - Nov 2005
Event	International Symposium on System-on-Chip, SoC 2005 - Tampere, Finland Duration: 14 Nov 2005 → 17 Nov 2005

Publication series

Name
Publisher	IEEE

Conference

Conference	International Symposium on System-on-Chip, SoC 2005
Abbreviated title	SoC
Country/Territory	Finland
City	Tampere
Period	14/11/05 → 17/11/05

Keywords

EWI-1670
IR-54759
METIS-229225
CAES-EEA: Efficient Embedded Architectures

Access to Document

10.1109/ISSOC.2005.1595648

Cite this

@inproceedings{928fb4ba9cf444d69dc7400fbf84fe3e,

title = "Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures",

abstract = "To improve power figures of a dual ARM9 RISC core architecture targeting low-power digital broadcasting applications, the addition of a coarse-grain architecture is considered. This paper introduces two of these structures: PACT's XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a Fast Fourier Transform on 1920 complex samples on both of them. Results in terms of processing time, resource utilization and energy dissipation are described and compared to those we have obtained on the RISC core. Then, as a conclusion, the paper presents the next steps of the development and some development issues.",

keywords = "EWI-1670, IR-54759, METIS-229225, CAES-EEA: Efficient Embedded Architectures",

author = "Arnaud Rivaton and J{\'e}r{\^o}me Quevremont and Q. Zhang and P.T. Wolkotte and Smit, {Gerardus Johannes Maria}",

note = "Imported from CHAMELEON.xml; International Symposium on System-on-Chip, SoC 2005 ; Conference date: 14-11-2005 Through 17-11-2005",

year = "2005",

month = nov,

doi = "10.1109/ISSOC.2005.1595648",

language = "Undefined",

isbn = "0-7803-9294-9",

publisher = "IEEE",

pages = "82--85",

editor = "J. Nurmi and J. Takala and T.D. Hamalainen",

booktitle = "Proceedings of the International Symposium on System-on-Chip (SoC 2005)",

address = "United States",

}

Rivaton, A, Quevremont, J, Zhang, Q, Wolkotte, PT & Smit, GJM 2005, Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures. in J Nurmi, J Takala & TD Hamalainen (eds), Proceedings of the International Symposium on System-on-Chip (SoC 2005). IEEE, Piscataway, New Jersey, USA, pp. 82-85, International Symposium on System-on-Chip, SoC 2005, Tampere, Finland, 14/11/05. https://doi.org/10.1109/ISSOC.2005.1595648

Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures. / Rivaton, Arnaud; Quevremont, Jérôme; Zhang, Q. et al.
Proceedings of the International Symposium on System-on-Chip (SoC 2005). ed. / J. Nurmi; J. Takala; T.D. Hamalainen. Piscataway, New Jersey, USA: IEEE, 2005. p. 82-85.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Wolkotte, P.T.

AU - Smit, Gerardus Johannes Maria

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N2 - To improve power figures of a dual ARM9 RISC core architecture targeting low-power digital broadcasting applications, the addition of a coarse-grain architecture is considered. This paper introduces two of these structures: PACT's XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a Fast Fourier Transform on 1920 complex samples on both of them. Results in terms of processing time, resource utilization and energy dissipation are described and compared to those we have obtained on the RISC core. Then, as a conclusion, the paper presents the next steps of the development and some development issues.

AB - To improve power figures of a dual ARM9 RISC core architecture targeting low-power digital broadcasting applications, the addition of a coarse-grain architecture is considered. This paper introduces two of these structures: PACT's XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a Fast Fourier Transform on 1920 complex samples on both of them. Results in terms of processing time, resource utilization and energy dissipation are described and compared to those we have obtained on the RISC core. Then, as a conclusion, the paper presents the next steps of the development and some development issues.

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