Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology

S. Yadav; A.B.J. Kokkeler; M.S. Oude Alink

doi:10.1109/ISCAS46773.2023.10181651

Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology

S. Yadav^*, A.B.J. Kokkeler, M.S. Oude Alink

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

High performance and energy efficiency are very crucial aspects in e.g. the field of edge computing where a tight power budget constrains the device operation. Different logic families were explored over the years to design standard cells with higher performance and/or lower power while keeping the noise immunity and the compatibility with design automation tools intact. Hybrid pass transistor logic with static CMOS output (HPSC) seems to be promising and is exploited in this paper to design low energy, high performance and toolchain-compatible standard cells without compromising on noise immunity and chip area. This paper presents a 2/3-input XOR cell, a 2/3-input XNOR cell, two variants of a half adder cell, a full adder cell and two variants of a 1-bit multiply-accumulate combinational cell based on a combination of HPSC and static CMOS logic in a commercial 65nm Low-Power CMOS technology. Post-layout simulations over all the process-voltage-temperature corners show a 4.7% - 35.7% lower energy-delay product with significant improvement in the propagation delay of the proposed cells

Original language	English
Title of host publication	2023 IEEE International Symposium on Circuits and Systems (ISCAS)
Place of Publication	Piscataway, NJ
Publisher	IEEE
Number of pages	5
ISBN (Electronic)	978-1-6654-5109-3
ISBN (Print)	978-1-6654-5110-9
DOIs	https://doi.org/10.1109/ISCAS46773.2023.10181651
Publication status	Published - 24 May 2023
Event	56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States Duration: 21 May 2023 → 25 May 2023 Conference number: 56

Publication series

Name	IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	IEEE
Volume	2023
ISSN (Print)	0271-4302
ISSN (Electronic)	2158-1525

Conference

Conference	56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Abbreviated title	ISCAS 2023
Country/Territory	United States
City	Monterey
Period	21/05/23 → 25/05/23

Keywords

Standard cell optimization
Cell design
Logic design
Super-threshold operation
Leakage power
Propagation delay
HPSC
PDP
EDP
Digital
CMOS
2023 OA procedure

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISCAS46773.2023.10181651

ArticleAccepted author version, 384 KB

Cite this

Yadav, S., Kokkeler, A. B. J., & Oude Alink, M. S. (2023). Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology. In 2023 IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE International Symposium on Circuits and Systems (ISCAS); Vol. 2023). IEEE. https://doi.org/10.1109/ISCAS46773.2023.10181651

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title = "Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology",

abstract = "High performance and energy efficiency are very crucial aspects in e.g. the field of edge computing where a tight power budget constrains the device operation. Different logic families were explored over the years to design standard cells with higher performance and/or lower power while keeping the noise immunity and the compatibility with design automation tools intact. Hybrid pass transistor logic with static CMOS output (HPSC) seems to be promising and is exploited in this paper to design low energy, high performance and toolchain-compatible standard cells without compromising on noise immunity and chip area. This paper presents a 2/3-input XOR cell, a 2/3-input XNOR cell, two variants of a half adder cell, a full adder cell and two variants of a 1-bit multiply-accumulate combinational cell based on a combination of HPSC and static CMOS logic in a commercial 65nm Low-Power CMOS technology. Post-layout simulations over all the process-voltage-temperature corners show a 4.7% - 35.7% lower energy-delay product with significant improvement in the propagation delay of the proposed cells ",

keywords = "Standard cell optimization, Cell design, Logic design, Super-threshold operation, Leakage power, Propagation delay, HPSC, PDP, EDP, Digital, CMOS, 2023 OA procedure",

author = "S. Yadav and A.B.J. Kokkeler and {Oude Alink}, M.S.",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023, ISCAS 2023 ; Conference date: 21-05-2023 Through 25-05-2023",

year = "2023",

month = may,

day = "24",

doi = "10.1109/ISCAS46773.2023.10181651",

language = "English",

isbn = "978-1-6654-5110-9",

series = "IEEE International Symposium on Circuits and Systems (ISCAS)",

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Yadav, S , Kokkeler, ABJ & Oude Alink, MS 2023, Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology. in 2023 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2023, IEEE, Piscataway, NJ, 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, California, United States, 21/05/23. https://doi.org/10.1109/ISCAS46773.2023.10181651

Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology. / Yadav, S.; Kokkeler, A.B.J.; Oude Alink, M.S.
2023 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway, NJ: IEEE, 2023. (IEEE International Symposium on Circuits and Systems (ISCAS); Vol. 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology

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AU - Kokkeler, A.B.J.

AU - Oude Alink, M.S.

N1 - Conference code: 56

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N2 - High performance and energy efficiency are very crucial aspects in e.g. the field of edge computing where a tight power budget constrains the device operation. Different logic families were explored over the years to design standard cells with higher performance and/or lower power while keeping the noise immunity and the compatibility with design automation tools intact. Hybrid pass transistor logic with static CMOS output (HPSC) seems to be promising and is exploited in this paper to design low energy, high performance and toolchain-compatible standard cells without compromising on noise immunity and chip area. This paper presents a 2/3-input XOR cell, a 2/3-input XNOR cell, two variants of a half adder cell, a full adder cell and two variants of a 1-bit multiply-accumulate combinational cell based on a combination of HPSC and static CMOS logic in a commercial 65nm Low-Power CMOS technology. Post-layout simulations over all the process-voltage-temperature corners show a 4.7% - 35.7% lower energy-delay product with significant improvement in the propagation delay of the proposed cells

AB - High performance and energy efficiency are very crucial aspects in e.g. the field of edge computing where a tight power budget constrains the device operation. Different logic families were explored over the years to design standard cells with higher performance and/or lower power while keeping the noise immunity and the compatibility with design automation tools intact. Hybrid pass transistor logic with static CMOS output (HPSC) seems to be promising and is exploited in this paper to design low energy, high performance and toolchain-compatible standard cells without compromising on noise immunity and chip area. This paper presents a 2/3-input XOR cell, a 2/3-input XNOR cell, two variants of a half adder cell, a full adder cell and two variants of a 1-bit multiply-accumulate combinational cell based on a combination of HPSC and static CMOS logic in a commercial 65nm Low-Power CMOS technology. Post-layout simulations over all the process-voltage-temperature corners show a 4.7% - 35.7% lower energy-delay product with significant improvement in the propagation delay of the proposed cells

KW - Standard cell optimization

KW - Cell design

KW - Logic design

KW - Super-threshold operation

KW - Leakage power

KW - Propagation delay

KW - HPSC

KW - PDP

KW - EDP

KW - Digital

KW - CMOS

KW - 2023 OA procedure

U2 - 10.1109/ISCAS46773.2023.10181651

DO - 10.1109/ISCAS46773.2023.10181651

M3 - Conference contribution

SN - 978-1-6654-5110-9

T3 - IEEE International Symposium on Circuits and Systems (ISCAS)

BT - 2023 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE

CY - Piscataway, NJ

T2 - 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023

Y2 - 21 May 2023 through 25 May 2023

ER -

Yadav S , Kokkeler ABJ , Oude Alink MS. Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology. In 2023 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway, NJ: IEEE. 2023. (IEEE International Symposium on Circuits and Systems (ISCAS)). doi: 10.1109/ISCAS46773.2023.10181651

Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology

Abstract

Publication series

Conference

Keywords

UN SDGs

Access to Document

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Cite this