Improving Performance of Hardware Accelerators by Optimizing Data Movement: A Bioinformatics Case Study

Peter Knoben, Nikolaos Alachiotis*

*Corresponding author for this work

Research output: Contribution to journalArticleAcademicpeer-review

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Abstract

Modern hardware accelerator cards create an accessible platform for developers to reduce execution times for computationally expensive algorithms. The most widely used systems, however, have dedicated memory spaces, resulting in the processor having to transfer data to the accelerator-card memory space before the computation can be executed. Currently, the performance increase from using an accelerator card for data-intensive algorithms is limited by the data movement. To this end, this work aims to reduce the effect of data movement and improve overall performance by systematically caching data on the accelerator card. We designed a software-controlled split cache where data are cached on the accelerator and assessed its efficacy using a data-intensive Bioinformatics application that infers the evolutionary history of a set of organisms by constructing phylogenetic trees. Our results revealed that software-controlled data caching on a datacenter-grade FPGA accelerator card reduced the overhead of data movement by 90%. This resulted in a reduction of the total execution time between 32% and 40% for the entire application when phylogenetic trees of various sizes were constructed.
Original languageEnglish
Article number586
JournalElectronics
Volume12
Issue number3
Early online date24 Jan 2023
DOIs
Publication statusPublished - 1 Feb 2023

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