Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes

Alessandro Palumbo; Luca Cassano; Pedro Reviriego; Marco Ottavi

doi:10.1109/DFT59622.2023.10313563

Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes

Alessandro Palumbo^*, Luca Cassano, Pedro Reviriego, Marco Ottavi

^*Corresponding author for this work

Digital Society Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Software-exploitable Hardware Trojan Horses (HTHs) can be inserted into commercial microprocessors allowing the attackers to run their own software or to gain unauthorized privileges. As a consequence, HTHs should nowadays be considered a serious threat not only by the academy but also by the industry. In this paper we present a hardware security checker for the detection of the runtime activation of HTHs. In particular, we aim at detecting HTHs that alter the expected execution flow by launching a malicious program. To achieve this goal the proposed checker is connected between the microprocessor and the main memory and observes the fetching activity. We integrated the proposed checker within a case study based on a RISC-V microprocessor running a set of software benchmarks. The experiment demonstrated that our checker is able to detect 100% of possible HTHs activations with no false alarms. We measured an area overhead of less than 1% w.r.t. LUTs and FFs with 8.5 up to 9.5 BRAM blocks required, a 2.51% power consumption increase, and no working frequency reduction.

Original language	English
Title of host publication	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Editors	Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio
Place of Publication	Piscataway, NJ
Publisher	IEEE
ISBN (Electronic)	9798350315004
DOIs	https://doi.org/10.1109/DFT59622.2023.10313563
Publication status	Published - 14 Nov 2023
Event	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 - Antipolis, at the Palais des Congrès d'Antibes, Juan-Les-Pins, France Duration: 3 Oct 2023 → 5 Oct 2023

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Volume	36
ISSN (Print)	2576-1501
ISSN (Electronic)	2765-933X

Conference

Conference	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Abbreviated title	DFT 2023
Country/Territory	France
City	Juan-Les-Pins
Period	3/10/23 → 5/10/23

Keywords

Hamming Codes
Hardware Security
Hardware Trojan Horses
Microprocessor-based System
RISC-V
NLA

Access to Document

10.1109/DFT59622.2023.10313563

Cite this

Palumbo, A., Cassano, L., Reviriego, P., & Ottavi, M. (2023). Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. In L. Cassano, M. Psarakis, M. Traiola, & A. Bosio (Eds.), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 36). IEEE. https://doi.org/10.1109/DFT59622.2023.10313563

Palumbo, Alessandro ; Cassano, Luca ; Reviriego, Pedro et al. / Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. editor / Luca Cassano ; Mihalis Psarakis ; Marcello Traiola ; Alberto Bosio. Piscataway, NJ : IEEE, 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

@inproceedings{162504aad411475aa8c238e74e8a2031,

title = "Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes",

abstract = "Software-exploitable Hardware Trojan Horses (HTHs) can be inserted into commercial microprocessors allowing the attackers to run their own software or to gain unauthorized privileges. As a consequence, HTHs should nowadays be considered a serious threat not only by the academy but also by the industry. In this paper we present a hardware security checker for the detection of the runtime activation of HTHs. In particular, we aim at detecting HTHs that alter the expected execution flow by launching a malicious program. To achieve this goal the proposed checker is connected between the microprocessor and the main memory and observes the fetching activity. We integrated the proposed checker within a case study based on a RISC-V microprocessor running a set of software benchmarks. The experiment demonstrated that our checker is able to detect 100% of possible HTHs activations with no false alarms. We measured an area overhead of less than 1% w.r.t. LUTs and FFs with 8.5 up to 9.5 BRAM blocks required, a 2.51% power consumption increase, and no working frequency reduction.",

keywords = "Hamming Codes, Hardware Security, Hardware Trojan Horses, Microprocessor-based System, RISC-V, NLA",

author = "Alessandro Palumbo and Luca Cassano and Pedro Reviriego and Marco Ottavi",

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Palumbo, A, Cassano, L, Reviriego, P & Ottavi, M 2023, Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. in L Cassano, M Psarakis, M Traiola & A Bosio (eds), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, vol. 36, IEEE, Piscataway, NJ, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, 3/10/23. https://doi.org/10.1109/DFT59622.2023.10313563

Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. / Palumbo, Alessandro; Cassano, Luca; Reviriego, Pedro et al.
36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. ed. / Luca Cassano; Mihalis Psarakis; Marcello Traiola; Alberto Bosio. Piscataway, NJ: IEEE, 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 36).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes

AU - Palumbo, Alessandro

AU - Cassano, Luca

AU - Reviriego, Pedro

AU - Ottavi, Marco

PY - 2023/11/14

Y1 - 2023/11/14

N2 - Software-exploitable Hardware Trojan Horses (HTHs) can be inserted into commercial microprocessors allowing the attackers to run their own software or to gain unauthorized privileges. As a consequence, HTHs should nowadays be considered a serious threat not only by the academy but also by the industry. In this paper we present a hardware security checker for the detection of the runtime activation of HTHs. In particular, we aim at detecting HTHs that alter the expected execution flow by launching a malicious program. To achieve this goal the proposed checker is connected between the microprocessor and the main memory and observes the fetching activity. We integrated the proposed checker within a case study based on a RISC-V microprocessor running a set of software benchmarks. The experiment demonstrated that our checker is able to detect 100% of possible HTHs activations with no false alarms. We measured an area overhead of less than 1% w.r.t. LUTs and FFs with 8.5 up to 9.5 BRAM blocks required, a 2.51% power consumption increase, and no working frequency reduction.

AB - Software-exploitable Hardware Trojan Horses (HTHs) can be inserted into commercial microprocessors allowing the attackers to run their own software or to gain unauthorized privileges. As a consequence, HTHs should nowadays be considered a serious threat not only by the academy but also by the industry. In this paper we present a hardware security checker for the detection of the runtime activation of HTHs. In particular, we aim at detecting HTHs that alter the expected execution flow by launching a malicious program. To achieve this goal the proposed checker is connected between the microprocessor and the main memory and observes the fetching activity. We integrated the proposed checker within a case study based on a RISC-V microprocessor running a set of software benchmarks. The experiment demonstrated that our checker is able to detect 100% of possible HTHs activations with no false alarms. We measured an area overhead of less than 1% w.r.t. LUTs and FFs with 8.5 up to 9.5 BRAM blocks required, a 2.51% power consumption increase, and no working frequency reduction.

KW - Hamming Codes

KW - Hardware Security

KW - Hardware Trojan Horses

KW - Microprocessor-based System

KW - RISC-V

KW - NLA

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DO - 10.1109/DFT59622.2023.10313563

M3 - Conference contribution

AN - SCOPUS:85179003050

T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT

BT - 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023

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A2 - Psarakis, Mihalis

A2 - Traiola, Marcello

A2 - Bosio, Alberto

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T2 - 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023

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Palumbo A, Cassano L, Reviriego P, Ottavi M. Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. In Cassano L, Psarakis M, Traiola M, Bosio A, editors, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Piscataway, NJ: IEEE. 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT59622.2023.10313563

Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes

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