Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration

Hasan Irmak, Daniel Ziener, Nikolaos Alachiotis

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Convolutional Neural Networks (CNN) are widely used for image classification and have achieved significantly accurate performance in the last decade. However, they require computationally intensive operations for embedded applications. In recent years, FPGA-based CNN accelerators have been proposed to improve energy efficiency and throughput. While dynamic partial reconfiguration (DPR) is increasingly used in CNN accelerators, the performance of dynamically reconfigurable accelerators is usually lower than the performance of pure static FPGA designs. This work presents a dynamically reconfigurable CNN accelerator architecture that does not sacrifice throughput performance or classification accuracy. The proposed accelerator is composed of reconfigurable macroblocks and dynamically utilizes the device resources according to model parameters. Moreover, we devise a novel approach, to the best of our knowledge, to hide the computations of the pooling layers inside the convolutional layers, thereby further improving throughput. Using the proposed architecture and DPR, different CNN architectures can be realized on the same FPGA with optimized throughput and accuracy. The proposed architecture is evaluated by implementing two different LeNet CNN models trained by different datasets and classifying different classes. Experimental results show that the implemented design achieves higher throughput than current LeNet FPGA accelerators.
Original languageEnglish
Title of host publication2021 31st International Conference on Field-Programmable Logic and Applications (FPL)
PublisherIEEE EDS
Pages306-311
Number of pages6
ISBN (Print)978-1-6654-4243-5
DOIs
Publication statusPublished - 12 Oct 2021
Event31st International Conference on Field-Programmable Logic and Applications (FPL) - Dresden, Germany, Virtual Conference
Duration: 30 Aug 20213 Sep 2021
Conference number: 31

Conference

Conference31st International Conference on Field-Programmable Logic and Applications (FPL)
Abbreviated titleFPL 2021
CityVirtual Conference
Period30/08/213/09/21

Keywords

  • Performance evaluation
  • Degradation
  • Computational modeling
  • Accelerator architectures
  • Switches
  • Throughput
  • Energy efficiency

Fingerprint

Dive into the research topics of 'Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration'. Together they form a unique fingerprint.

Cite this