TY - GEN
T1 - Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration
AU - Asghar, Ali
AU - Hettwer, Benjamin
AU - Karimov, Emil
AU - Ziener, Daniel
N1 - Funding Information:
This work has been supported by the German Federal Ministry for Eduction and Research (BMBF) within the collaborative research project ?SecRec? (16KIS0609).
Publisher Copyright:
© 2021, Springer Nature Switzerland AG.
PY - 2021/6/23
Y1 - 2021/6/23
N2 - Modern FPGAs are equipped with the possibility of Partial Reconfiguration (PR) which along with other benefits can be used to enhance the security of cryptographic implementations. This feature requires development of alternative designs to be exchanged during run-time. In this work, we propose dynamically alterable circuits by exploring netlist randomization which can be utilized with PR as a countermeasure against physical attacks, in particular side-channel attacks. The proposed approach involves modification of an AES implementation at the netlist level in order to create circuit variants which are functionally identical but structurally different. In preliminary experiments, power traces of these variants have been shuffled to replicate the effect of partial reconfiguration. With these dynamic circuits, our experimental results show an increase in the resistance against power side-channel attacks by a factor of ∼ 12.6 on a Xilinx ZYNQ UltraScale+ device.
AB - Modern FPGAs are equipped with the possibility of Partial Reconfiguration (PR) which along with other benefits can be used to enhance the security of cryptographic implementations. This feature requires development of alternative designs to be exchanged during run-time. In this work, we propose dynamically alterable circuits by exploring netlist randomization which can be utilized with PR as a countermeasure against physical attacks, in particular side-channel attacks. The proposed approach involves modification of an AES implementation at the netlist level in order to create circuit variants which are functionally identical but structurally different. In preliminary experiments, power traces of these variants have been shuffled to replicate the effect of partial reconfiguration. With these dynamic circuits, our experimental results show an increase in the resistance against power side-channel attacks by a factor of ∼ 12.6 on a Xilinx ZYNQ UltraScale+ device.
KW - FPGAs
KW - Partial reconfiguration
KW - Power analysis attacks
KW - Side-channel attacks
UR - http://www.scopus.com/inward/record.url?scp=85112653929&partnerID=8YFLogxK
U2 - 10.1007/978-3-030-79025-7_12
DO - 10.1007/978-3-030-79025-7_12
M3 - Conference contribution
AN - SCOPUS:85112653929
SN - 9783030790240
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 173
EP - 187
BT - Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Proceedings
A2 - Derrien, Steven
A2 - Hannig, Frank
A2 - Diniz, Pedro C.
A2 - Chillet, Daniel
PB - Springer
T2 - 17th International Symposium on Applied Reconfigurable Computing, ARC 2021
Y2 - 29 June 2021 through 30 June 2021
ER -