Increasing SoC Dependability via Known Good Tile NoC Testing

Hans G. Kerkhoff, O.J. Kuiken, X. Zhang

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Abstract

    Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitating dependable designs [2]. Our approach for a dependable SoC heavily depends on the regularity within our streaming-data applications SoC. The chip consists of many identical NoC segments and identical PT’s. Boundary condition is that target applications do not require all available fault-free resources, such as routing segments and PTs.
    Original languageUndefined
    Title of host publicationFastAbs Track of The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN2008)
    Place of PublicationPiscataway
    Publisherunpublished
    PagesPaper 14
    Number of pages2
    ISBN (Print)not assigned
    Publication statusPublished - 25 Jun 2008
    EventFastAbs Track of The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN2008) - Anchorage, Alaska
    Duration: 24 Jun 200927 Jun 2009

    Publication series

    Name
    PublisherIEEE Computer Society Press
    Number2008/16200

    Conference

    ConferenceFastAbs Track of The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN2008)
    Period24/06/0927/06/09
    Other24-27 June 2009

    Keywords

    • EWI-14790
    • METIS-255074
    • IR-62663

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