Increasing SoC Dependability via Known Good Tile NoC Testing

Hans G. Kerkhoff; Oscar J. Kuiken; Xiao Zhang

Increasing SoC Dependability via Known Good Tile NoC Testing

Hans G. Kerkhoff
, Oscar J. Kuiken
, Xiao Zhang

Research output: Contribution to conference › Paper › peer-review

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Abstract

Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitating dependable designs [2]. Our approach for a dependable SoC heavily depends on the regularity within our streaming-data applications SoC. The chip consists of many identical NoC segments and identical PT’s. Boundary condition is that target applications do not require all available fault-free resources, such as routing segments and PTs.

Original language	English
Number of pages	2
Publication status	Published - 25 Jun 2008
Event	38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008 - Anchorage, United States Duration: 24 Jun 2008 → 27 Jun 2008 Conference number: 38

Conference

Conference	38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008
Abbreviated title	DSN
Country/Territory	United States
City	Anchorage
Period	24/06/08 → 27/06/08

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http://www.ece.cmu.edu/~koopman/dsn08/fastabs.html

Cite this

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title = "Increasing SoC Dependability via Known Good Tile NoC Testing",

abstract = "Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitating dependable designs [2]. Our approach for a dependable SoC heavily depends on the regularity within our streaming-data applications SoC. The chip consists of many identical NoC segments and identical PT{\textquoteright}s. Boundary condition is that target applications do not require all available fault-free resources, such as routing segments and PTs.",

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T1 - Increasing SoC Dependability via Known Good Tile NoC Testing

AU - Kerkhoff, Hans G.

AU - Kuiken, Oscar J.

AU - Zhang, Xiao

N1 - Conference code: 38

PY - 2008/6/25

Y1 - 2008/6/25

N2 - Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitating dependable designs [2]. Our approach for a dependable SoC heavily depends on the regularity within our streaming-data applications SoC. The chip consists of many identical NoC segments and identical PT’s. Boundary condition is that target applications do not require all available fault-free resources, such as routing segments and PTs.

AB - Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitating dependable designs [2]. Our approach for a dependable SoC heavily depends on the regularity within our streaming-data applications SoC. The chip consists of many identical NoC segments and identical PT’s. Boundary condition is that target applications do not require all available fault-free resources, such as routing segments and PTs.

M3 - Paper

T2 - 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008

Y2 - 24 June 2008 through 27 June 2008

ER -

Increasing SoC Dependability via Known Good Tile NoC Testing

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Conference

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