In this work, we have studied the performance of CMOS chips before and after a low temperature post-processing step. In order to prevent damage to the IC chips by the post-processing steps, a first passivation layers is needed on top of the IC chips. Two different passivation layer deposition technologies have been evaluated: magnetron-sputtered Ti/W and PECVD SiOx/SiNx layer stack. After the passivation, the IC chip underwent thermal annealing for 30 minutes at 400oC in N2 atmosphere. In the final step, the passivation layer has been removed by wet-etching, to enable measuring the chip after post-processing. Electrical measurements of the chip performance were carried out before and after post-processing, to evaluate the influence of the passivation step. We observed a small threshold voltage shift due to plasma processing, but the value are close to statistical variation. Therefore the passivation layer stack deposition can hardly influence the performance of the CMOS chip. This offers a possibility of further post-processing of such IC chips.
|Title of host publication||Proceedings of the 12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors|
|Place of Publication||Utrecht, The Netherlands|
|Number of pages||3|
|Publication status||Published - 26 Nov 2009|
|Event||12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2009 - Veldhoven, Netherlands|
Duration: 26 Nov 2009 → 27 Nov 2009
Conference number: 12
|Publisher||Technology Foundation STW|
|Conference||12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2009|
|Period||26/11/09 → 27/11/09|
- CMOS post-processing
- plasma damage
- SC-DPM: Device Physics and Modeling
- plasma charge
Lu, J., Kovalgin, A. Y., & Schmitz, J. (2009). Influence of passivation process on chip performance. In Proceedings of the 12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors (pp. 542-544). Utrecht, The Netherlands: STW.