Influence of passivation process on chip performance

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

    Abstract

    In this work, we have studied the performance of CMOS chips before and after a low temperature post-processing step. In order to prevent damage to the IC chips by the post-processing steps, a first passivation layers is needed on top of the IC chips. Two different passivation layer deposition technologies have been evaluated: magnetron-sputtered Ti/W and PECVD SiOx/SiNx layer stack. After the passivation, the IC chip underwent thermal annealing for 30 minutes at 400oC in N2 atmosphere. In the final step, the passivation layer has been removed by wet-etching, to enable measuring the chip after post-processing. Electrical measurements of the chip performance were carried out before and after post-processing, to evaluate the influence of the passivation step. We observed a small threshold voltage shift due to plasma processing, but the value are close to statistical variation. Therefore the passivation layer stack deposition can hardly influence the performance of the CMOS chip. This offers a possibility of further post-processing of such IC chips.
    Original languageUndefined
    Title of host publicationProceedings of the 12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors
    Place of PublicationUtrecht, The Netherlands
    PublisherSTW
    Pages542-544
    Number of pages3
    ISBN (Print)978-90-73461-62-8
    Publication statusPublished - 26 Nov 2009
    Event12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2009 - Veldhoven, Netherlands
    Duration: 26 Nov 200927 Nov 2009
    Conference number: 12

    Publication series

    Name
    PublisherTechnology Foundation STW

    Conference

    Conference12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2009
    Abbreviated titleSAFE
    CountryNetherlands
    CityVeldhoven
    Period26/11/0927/11/09

    Keywords

    • IR-69053
    • METIS-264266
    • CMOS post-processing
    • EWI-17052
    • plasma damage
    • SC-DPM: Device Physics and Modeling
    • plasma charge

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