Influence of passivation process on chip performance

J. Lu; Alexeij Y. Kovalgin; Jurriaan Schmitz

Influence of passivation process on chip performance

J. Lu, Alexeij Y. Kovalgin, Jurriaan Schmitz

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic

Abstract

In this work, we have studied the performance of CMOS chips before and after a low temperature post-processing step. In order to prevent damage to the IC chips by the post-processing steps, a first passivation layers is needed on top of the IC chips. Two different passivation layer deposition technologies have been evaluated: magnetron-sputtered Ti/W and PECVD SiOx/SiNx layer stack. After the passivation, the IC chip underwent thermal annealing for 30 minutes at 400oC in N2 atmosphere. In the final step, the passivation layer has been removed by wet-etching, to enable measuring the chip after post-processing. Electrical measurements of the chip performance were carried out before and after post-processing, to evaluate the influence of the passivation step. We observed a small threshold voltage shift due to plasma processing, but the value are close to statistical variation. Therefore the passivation layer stack deposition can hardly influence the performance of the CMOS chip. This offers a possibility of further post-processing of such IC chips.

Original language	Undefined
Title of host publication	Proceedings of the 12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors
Place of Publication	Utrecht, The Netherlands
Publisher	STW
Pages	542-544
Number of pages	3
ISBN (Print)	978-90-73461-62-8
Publication status	Published - 26 Nov 2009
Event	12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2009 - Veldhoven, Netherlands Duration: 26 Nov 2009 → 27 Nov 2009 Conference number: 12

Publication series

Name
Publisher	Technology Foundation STW

Conference

Conference	12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2009
Abbreviated title	SAFE
Country/Territory	Netherlands
City	Veldhoven
Period	26/11/09 → 27/11/09

Keywords

IR-69053
METIS-264266
CMOS post-processing
EWI-17052
plasma damage
SC-DPM: Device Physics and Modeling
plasma charge

Access to Document

http://eprints.eemcs.utwente.nl/secure2/17052/01/lu.pdf

Cite this

@inproceedings{4124c4047b2d47e28fe257ae5fe037d3,

title = "Influence of passivation process on chip performance",

abstract = "In this work, we have studied the performance of CMOS chips before and after a low temperature post-processing step. In order to prevent damage to the IC chips by the post-processing steps, a first passivation layers is needed on top of the IC chips. Two different passivation layer deposition technologies have been evaluated: magnetron-sputtered Ti/W and PECVD SiOx/SiNx layer stack. After the passivation, the IC chip underwent thermal annealing for 30 minutes at 400oC in N2 atmosphere. In the final step, the passivation layer has been removed by wet-etching, to enable measuring the chip after post-processing. Electrical measurements of the chip performance were carried out before and after post-processing, to evaluate the influence of the passivation step. We observed a small threshold voltage shift due to plasma processing, but the value are close to statistical variation. Therefore the passivation layer stack deposition can hardly influence the performance of the CMOS chip. This offers a possibility of further post-processing of such IC chips.",

keywords = "IR-69053, METIS-264266, CMOS post-processing, EWI-17052, plasma damage, SC-DPM: Device Physics and Modeling, plasma charge",

author = "J. Lu and Kovalgin, {Alexeij Y.} and Jurriaan Schmitz",

year = "2009",

month = nov,

day = "26",

language = "Undefined",

isbn = "978-90-73461-62-8",

publisher = "STW",

pages = "542--544",

booktitle = "Proceedings of the 12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors",

note = "null ; Conference date: 26-11-2009 Through 27-11-2009",

}

Lu, J, Kovalgin, AY & Schmitz, J 2009, Influence of passivation process on chip performance. in Proceedings of the 12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors. STW, Utrecht, The Netherlands, pp. 542-544, 12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2009, Veldhoven, Netherlands, 26/11/09. <http://eprints.eemcs.utwente.nl/secure2/17052/01/lu.pdf>

TY - GEN

T1 - Influence of passivation process on chip performance

AU - Lu, J.

AU - Kovalgin, Alexeij Y.

AU - Schmitz, Jurriaan

N1 - Conference code: 12

PY - 2009/11/26

Y1 - 2009/11/26

N2 - In this work, we have studied the performance of CMOS chips before and after a low temperature post-processing step. In order to prevent damage to the IC chips by the post-processing steps, a first passivation layers is needed on top of the IC chips. Two different passivation layer deposition technologies have been evaluated: magnetron-sputtered Ti/W and PECVD SiOx/SiNx layer stack. After the passivation, the IC chip underwent thermal annealing for 30 minutes at 400oC in N2 atmosphere. In the final step, the passivation layer has been removed by wet-etching, to enable measuring the chip after post-processing. Electrical measurements of the chip performance were carried out before and after post-processing, to evaluate the influence of the passivation step. We observed a small threshold voltage shift due to plasma processing, but the value are close to statistical variation. Therefore the passivation layer stack deposition can hardly influence the performance of the CMOS chip. This offers a possibility of further post-processing of such IC chips.

AB - In this work, we have studied the performance of CMOS chips before and after a low temperature post-processing step. In order to prevent damage to the IC chips by the post-processing steps, a first passivation layers is needed on top of the IC chips. Two different passivation layer deposition technologies have been evaluated: magnetron-sputtered Ti/W and PECVD SiOx/SiNx layer stack. After the passivation, the IC chip underwent thermal annealing for 30 minutes at 400oC in N2 atmosphere. In the final step, the passivation layer has been removed by wet-etching, to enable measuring the chip after post-processing. Electrical measurements of the chip performance were carried out before and after post-processing, to evaluate the influence of the passivation step. We observed a small threshold voltage shift due to plasma processing, but the value are close to statistical variation. Therefore the passivation layer stack deposition can hardly influence the performance of the CMOS chip. This offers a possibility of further post-processing of such IC chips.

KW - IR-69053

KW - METIS-264266

KW - CMOS post-processing

KW - EWI-17052

KW - plasma damage

KW - SC-DPM: Device Physics and Modeling

KW - plasma charge

M3 - Conference contribution

SN - 978-90-73461-62-8

SP - 542

EP - 544

BT - Proceedings of the 12th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors

PB - STW

CY - Utrecht, The Netherlands

Y2 - 26 November 2009 through 27 November 2009

ER -