Integration of laser-annealed junctions in a low-temperature high-k metal-gate MISFET

Cleber Biasotto*, Vladimir Jovanović, Viktor Gonda, Johan Van Der Cingel, Silvana Milosavljević, Lis K. Nanver

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)

Abstract

Integration and properties of devices processed by excimer laser annealing are presented. The best results are achieved by shallow implantations into a native-oxide-free silicon surface and laser annealing with the remainder of the device protected by an Al reflective layer. Low-temperature MISFETs are fabricated with a metal-gate high-k gate stack of PECVD SiO2 and ALD Al2O3 with an EOT of 9.2 nm and an Al-gate. The source/drain regions are self-aligned to the metal gate, which also serves as a laser masking reflective layer. Ablation of the masking layer is prevented due to the low thermal resistance of the thin underlying gate dielectric. The measured devices exhibit good current drivability, which improves with higher laser energy. The maximum processing temperature of the presented MISFETs is 400° C and can potentially to be reduced down to 300°C.

Original languageEnglish
Title of host publicationProceedings of the 10th International Conference on ULtimate Integration of Silicon, ULIS 2009
Pages181-184
Number of pages4
DOIs
Publication statusPublished - 23 Jul 2009
Externally publishedYes
Event10th International Conference on ULtimate Integration of Silicon, ULIS 2009 - Aachen, Germany
Duration: 18 Mar 200920 Mar 2009
Conference number: 10

Conference

Conference10th International Conference on ULtimate Integration of Silicon, ULIS 2009
Abbreviated titleULIS
CountryGermany
CityAachen
Period18/03/0920/03/09

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Biasotto, C., Jovanović, V., Gonda, V., Van Der Cingel, J., Milosavljević, S., & Nanver, L. K. (2009). Integration of laser-annealed junctions in a low-temperature high-k metal-gate MISFET. In Proceedings of the 10th International Conference on ULtimate Integration of Silicon, ULIS 2009 (pp. 181-184). [4897566] https://doi.org/10.1109/ULIS.2009.4897566