Integration of Physical Reliability Knowledge into the Design of VLSI-Circuits

D.C.L. van Geest; R.H. Hoeksma; A.C. Brombacher; O.E. Herrmann

doi:10.1109/RELPHY.1993.283297

Integration of Physical Reliability Knowledge into the Design of VLSI-Circuits

D.C.L. van Geest, R.H. Hoeksma, A.C. Brombacher, O.E. Herrmann

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A systematic approach for modeling failure mechanisms on the circuit level and for using these models for optimization of both reliability and functionability is presented. Since optimization is done using a CAD system, it is possible to carry out such an optimization in a very early stage of the design process. The stress factors of the failure mechanisms are calculated using a circuit simulator and the effect of internal and external tolerances is incorporated in the simulation. From these results the sensitivity of failure behavior for so-called designable parameters on circuit level is determined. This information is used to optimize the design toward minimum occurrence of failures. For functional demands the same methodology is used

Original language	English
Title of host publication	31st Annual Proceedings Reliability Physics 1993
Subtitle of host publication	Atlanta, Georgia March 23, 24, 25, 1993
Publisher	IEEE
Pages	81-86
Number of pages	6
ISBN (Print)	0-7803-0782-8, 0-7803-0783-6
DOIs	https://doi.org/10.1109/RELPHY.1993.283297
Publication status	Published - 1 Sep 1993
Event	31st Annual IEEE International Reliability Physics Symposium, IRPS 1993 - Atlanta, United States Duration: 23 Mar 1993 → 25 Mar 1993 Conference number: 31

Conference

Conference	31st Annual IEEE International Reliability Physics Symposium, IRPS 1993
Abbreviated title	IRPS
Country/Territory	United States
City	Atlanta
Period	23/03/93 → 25/03/93

Keywords

METIS-113106
IR-16221

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10.1109/RELPHY.1993.283297

Integration of Physical Reliability KnowledgeFinal published version, 517 KB

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title = "Integration of Physical Reliability Knowledge into the Design of VLSI-Circuits",

abstract = "A systematic approach for modeling failure mechanisms on the circuit level and for using these models for optimization of both reliability and functionability is presented. Since optimization is done using a CAD system, it is possible to carry out such an optimization in a very early stage of the design process. The stress factors of the failure mechanisms are calculated using a circuit simulator and the effect of internal and external tolerances is incorporated in the simulation. From these results the sensitivity of failure behavior for so-called designable parameters on circuit level is determined. This information is used to optimize the design toward minimum occurrence of failures. For functional demands the same methodology is used",

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author = "{van Geest}, D.C.L. and R.H. Hoeksma and A.C. Brombacher and O.E. Herrmann",

year = "1993",

month = sep,

day = "1",

doi = "10.1109/RELPHY.1993.283297",

language = "English",

isbn = "0-7803-0782-8",

pages = "81--86",

booktitle = "31st Annual Proceedings Reliability Physics 1993",

publisher = "IEEE",

note = "31st Annual IEEE International Reliability Physics Symposium, IRPS 1993, IRPS ; Conference date: 23-03-1993 Through 25-03-1993",

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van Geest, DCL, Hoeksma, RH, Brombacher, AC & Herrmann, OE 1993, Integration of Physical Reliability Knowledge into the Design of VLSI-Circuits. in 31st Annual Proceedings Reliability Physics 1993: Atlanta, Georgia March 23, 24, 25, 1993. IEEE, pp. 81-86, 31st Annual IEEE International Reliability Physics Symposium, IRPS 1993, Atlanta, Georgia, United States, 23/03/93. https://doi.org/10.1109/RELPHY.1993.283297

Integration of Physical Reliability Knowledge into the Design of VLSI-Circuits. / van Geest, D.C.L.; Hoeksma, R.H.; Brombacher, A.C. et al.

31st Annual Proceedings Reliability Physics 1993: Atlanta, Georgia March 23, 24, 25, 1993. IEEE, 1993. p. 81-86.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Integration of Physical Reliability Knowledge into the Design of VLSI-Circuits

AU - van Geest, D.C.L.

AU - Hoeksma, R.H.

AU - Brombacher, A.C.

AU - Herrmann, O.E.

N1 - Conference code: 31

PY - 1993/9/1

Y1 - 1993/9/1

N2 - A systematic approach for modeling failure mechanisms on the circuit level and for using these models for optimization of both reliability and functionability is presented. Since optimization is done using a CAD system, it is possible to carry out such an optimization in a very early stage of the design process. The stress factors of the failure mechanisms are calculated using a circuit simulator and the effect of internal and external tolerances is incorporated in the simulation. From these results the sensitivity of failure behavior for so-called designable parameters on circuit level is determined. This information is used to optimize the design toward minimum occurrence of failures. For functional demands the same methodology is used

AB - A systematic approach for modeling failure mechanisms on the circuit level and for using these models for optimization of both reliability and functionability is presented. Since optimization is done using a CAD system, it is possible to carry out such an optimization in a very early stage of the design process. The stress factors of the failure mechanisms are calculated using a circuit simulator and the effect of internal and external tolerances is incorporated in the simulation. From these results the sensitivity of failure behavior for so-called designable parameters on circuit level is determined. This information is used to optimize the design toward minimum occurrence of failures. For functional demands the same methodology is used

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KW - IR-16221

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M3 - Conference contribution

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SN - 0-7803-0783-6

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PB - IEEE

T2 - 31st Annual IEEE International Reliability Physics Symposium, IRPS 1993

Y2 - 23 March 1993 through 25 March 1993

ER -

Integration of Physical Reliability Knowledge into the Design of VLSI-Circuits

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