Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current

Matthias L. Vermeer; Raymond J.E. Hueting; Luca Pirro; Jan Hoentschel; Jurriaan Schmitz

doi:10.1109/TED.2020.3043223

Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current

Matthias L. Vermeer, Raymond J.E. Hueting, Luca Pirro, Jan Hoentschel, Jurriaan Schmitz

Research output: Contribution to journal › Article › Academic › peer-review

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Abstract

Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed gₘ/ID method with a revised form of the k-sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of 2 · 10¹¹ cm⁻²eV⁻². Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.

Original language	English
Article number	9305941
Pages (from-to)	497-502
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	68
Issue number	2
Early online date	23 Dec 2020
DOIs	https://doi.org/10.1109/TED.2020.3043223
Publication status	Published - 1 Feb 2021

Keywords

Capacitance
FinFETs
Ideality
Interface states
Logic gates
MOS transistors
Silicon
Silicon devices
Silicon on insulator
Silicon-on-insulator
Subthreshold
Transistors
Traps
silicon on insulator
traps.
interface states
silicon devices
subthreshold

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10.1109/TED.2020.3043223Licence: CC BY-NC-ND

ArticleFinal published version, 1.55 MBLicence: CC BY-NC-ND

Cite this

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title = "Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current",

abstract = "Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed gₘ/ID method with a revised form of the k-sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of 2 · 10¹¹ cm⁻²eV⁻². Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.",

keywords = "Capacitance, FinFETs, Ideality, Interface states, Logic gates, MOS transistors, Silicon, Silicon devices, Silicon on insulator, Silicon-on-insulator, Subthreshold, Transistors, Traps, silicon on insulator, traps., interface states, silicon devices, subthreshold",

author = "Vermeer, {Matthias L.} and Hueting, {Raymond J.E.} and Luca Pirro and Jan Hoentschel and Jurriaan Schmitz",

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AU - Vermeer, Matthias L.

AU - Hueting, Raymond J.E.

AU - Pirro, Luca

AU - Hoentschel, Jan

AU - Schmitz, Jurriaan

PY - 2021/2/1

Y1 - 2021/2/1

N2 - Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed gₘ/ID method with a revised form of the k-sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of 2 · 10¹¹ cm⁻²eV⁻². Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.

AB - Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed gₘ/ID method with a revised form of the k-sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of 2 · 10¹¹ cm⁻²eV⁻². Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.

KW - Capacitance

KW - FinFETs

KW - Ideality

KW - Interface states

KW - Logic gates

KW - MOS transistors

KW - Silicon

KW - Silicon devices

KW - Silicon on insulator

KW - Silicon-on-insulator

KW - Subthreshold

KW - Transistors

KW - Traps

KW - silicon on insulator

KW - traps.

KW - interface states

KW - silicon devices

KW - subthreshold

U2 - 10.1109/TED.2020.3043223

DO - 10.1109/TED.2020.3043223

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 2

M1 - 9305941

ER -

Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current

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Keywords

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