Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current

Matthias L. Vermeer, Raymond J.E. Hueting, Luca Pirro, Jan Hoentschel, Jurriaan Schmitz

    Research output: Contribution to journalArticleAcademicpeer-review

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    Abstract

    Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed gₘ/ID method with a revised form of the k-sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of 2 · 10¹¹ cm⁻²eV⁻². Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.
    Original languageEnglish
    Number of pages6
    JournalIEEE transactions on electron devices
    DOIs
    Publication statusE-pub ahead of print/First online - 23 Dec 2020

    Keywords

    • Capacitance
    • FinFETs
    • Ideality
    • Interface states
    • Logic gates
    • MOS transistors
    • Silicon
    • Silicon devices
    • Silicon on insulator
    • Silicon-on-insulator
    • Subthreshold
    • Transistors
    • Traps

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