Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current

Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed gₘ/ID method with a revised form of the k-sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of 2 · 10¹¹ cm⁻²eV⁻². Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.