Abstract
In this work we present a measurement approach to determine the interface trap density in FinFETs as a function of their energy. It is based on the precise determination of the gate voltage dependent ideality factor of the subthreshold current in this device. The required measurement accuracy for temperature, drain current and transconductance is derived, and we propose an implementation for wafer-level device measurement on contemporary test set-ups. Exemplary interface trap distributions are shown as obtained from two FinFET device technologies, featuring the commonly observed bathtub shape.
Original language | English |
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Title of host publication | 2016 International Conference on Microelectronic Test Structures (ICMTS) |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 164-167 |
Number of pages | 4 |
ISBN (Electronic) | 978-1-4673-8793-4 , 978-1-4673-8792-7 |
ISBN (Print) | 978-1-4673-8791-0 |
DOIs | |
Publication status | Published - 28 Mar 2016 |
Event | 29th International Conference on Microelectronic Test Structures, ICMTS 2016 - Mielparque Yokohama, Yokohama, Japan Duration: 28 Mar 2016 → 31 Mar 2016 Conference number: 29 |
Publication series
Name | Proceedings International Conference on Microelectronic Test Structures (ICMTS) |
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Publisher | IEEE |
Volume | 2016 |
ISSN (Print) | 1071-9032 |
ISSN (Electronic) | 2158-1029 |
Conference
Conference | 29th International Conference on Microelectronic Test Structures, ICMTS 2016 |
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Abbreviated title | ICMTS |
Country/Territory | Japan |
City | Yokohama |
Period | 28/03/16 → 31/03/16 |
Keywords
- Interface states
- MOS devices
- Traps
- Complementary MOSFETs (CMOSFETs)
- Current
- FinFETs