Interfacing Networks-on-Chip: Hardware meeting Software

M.D. van de Burgwal

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    138 Downloads (Pure)

    Abstract

    Next generation multi-media broadcast standards use encoded high-bandwidth streams of data to efficiently utilize the spectrum, at the cost of computation intensive processing. For battery powered portable devices this is challenging, as the energy source has limited capacity. By optimizing the computationally intensive kernels within an application, the energy consumption can be reduced significantly. A highly parallel Multi-processor System-on-Chip architecture is proposed, consisting of processors which communicate over Network-on-Chip via a Network Interface, a component that converts the communication protocols and synchronizes the processor and network. With multiple processors on a single chip, the available processing power increases and the processors can be used simultaneously. Another advantage of using a multi-processor architecture besides parallel processing, is concurrency in computation and communication. To utilize this concurrency efficiently, the Network Interface should support this concurrency. The programming model for such an architecture differs from conventional single processor systems. Partitioning of the applications into multiple concurrent threads is important to obtain high utilization of the computational resources. The application can be modeled as a set of independent kernels connected by communication channels, where kernels are mapped on processors, and communication channels are mapped on the Network-on-Chip. In this thesis, the design flow that enables modeling of streaming applications is discussed. The application model is based on a functional programming language, which has a strong resemblance with mathematics such that the application can be gradually translated from a mathematical specification to a partitioned realization. To verify the performance of a mapped application, a simulation model is created containing information about the application and architecture model. To illustrate the efficiency of the presented Network Interface and to demonstrate the data flow modeling technique, two wireless communication receivers are discussed. One receiver is a Digital Radio Mondiale receiver for handheld devices, where energy-efficiency is a key design goal, and the other is a Digital Video Broadcast for Satellite receiver targeting at the car infotainment domain. Both receivers are implemented on the same Multi-processor System-on-Chip, to show that such architectures are flexible for running different applications.
    Original languageEnglish
    Awarding Institution
    • University of Twente
    Supervisors/Advisors
    • Smit, Gerardus Johannes Maria, Supervisor
    • Kokkeler, Andre B.J., Co-Supervisor
    • Kuper, Jan , Co-Supervisor
    Award date15 Oct 2010
    Place of PublicationEnschede
    Publisher
    Print ISBNs978-90-365-3067-5
    DOIs
    Publication statusPublished - 15 Oct 2010

    Keywords

    • CAES-EEA: Efficient Embedded Architectures
    • EWI-18605
    • IR-73644
    • METIS-271073

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  • Cite this

    van de Burgwal, M. D. (2010). Interfacing Networks-on-Chip: Hardware meeting Software. Enschede: Centre for Telematics and Information Technology (CTIT). https://doi.org/10.3990/1.9789036530675