Interpretation of MOS transistor mismatch signature through statistical device simulations

Pietro Andricciola, P. Andricciola

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    110 Downloads (Pure)

    Abstract

    Semiconductor manufacturers daily fabricate millions of nominally identical integrated circuits made of supposedly identical components. However controlled the fabrication process can be, two components will always be slightly different when thoroughly compared. The comparison between two components is usually done using a certain parameter as estimator of the integrated circuit (IC) or transistor performance, e.g. a frequency of an oscillator or a current delivered by a transistor. What happens in reality is, for instance, that the frequencies of the identical oscillators fabricated, with the same process but in different foundries, or in different moments in the same foundry, will be different. Actually, even chips fabricated on the same wafer will not be exactly the same, as some fundamental characteristics of the fabrication process vary across the wafer. These sorts of variability are often deterministic. This means that a clear pattern appears after a significant number of observations
    Original languageUndefined
    Awarding Institution
    • University of Twente
    Supervisors/Advisors
    • Schmitz, Jurriaan, Supervisor
    • Tuinhout, H.P., Advisor, External person
    Thesis sponsors
    Award date21 Dec 2011
    Place of PublicationEnschede
    Publisher
    Print ISBNs978-90-365-3289-1
    DOIs
    Publication statusPublished - 21 Dec 2011

    Keywords

    • EWI-21149
    • IR-79245
    • METIS-284955

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