Inverter Chain Buffer Optimization for N-path Filter Switch Drivers and Validation through Simulations in 22nm FD-SOI Technology

In this paper, the CMOS inverter chain buffer is optimized for N-path filter switch drivers in a technology-agnostic way. Figures-of-merit are proposed to minimize jitter for minimal power dissipation with consideration of rise/fall-time. Using these, mathematical models are derived based on a simple circuit model and expressed for optimization as a function of the technology-specific inverter output/input capacitance ratio, the number of inverters, and their taper factors. This enables finding designs with any set of taper factors that have lower jitter than common designs for the same power dissipation by sweeping many designs orders of magnitude faster than using circuit simulations. Additionally, analytical equations are derived to quickly allow a designer to find the optimal number and sizing of inverters for the constant and exponential taper designs, either of which is shown to be near-optimal depending on the set of specifications