Inverter Chain Buffer Optimization for N-path Filter Switch Drivers and Validation through Simulations in 22nm FD-SOI Technology

Wouter Overeem*, Mark Stefan Oude Alink, Bram Nauta

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

In this paper, the CMOS inverter chain buffer is optimized for N-path filter switch drivers in a technology-agnostic way. Figures-of-merit are proposed to minimize jitter for minimal power dissipation with consideration of rise/fall-time. Using these, mathematical models are derived based on a simple circuit model and expressed for optimization as a function of the technology-specific inverter output/input capacitance ratio, the number of inverters, and their taper factors. This enables finding designs with any set of taper factors that have lower jitter than common designs for the same power dissipation by sweeping many designs orders of magnitude faster than using circuit simulations. Additionally, analytical equations are derived to quickly allow a designer to find the optimal number and sizing of inverters for the constant and exponential taper designs, either of which is shown to be near-optimal depending on the set of specifications
Original languageEnglish
Title of host publication2023 IEEE International Symposium on Circuits and Systems (ISCAS)
Place of PublicationMonterey, CA, USA
ISBN (Electronic)978-1-6654-5109-3
DOIs
Publication statusPublished - 21 Jul 2023
Event56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States
Duration: 21 May 202325 May 2023
Conference number: 56

Conference

Conference56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Abbreviated titleISCAS 2023
Country/TerritoryUnited States
CityMonterey
Period21/05/2325/05/23

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