Is RISC-V ready for Space? A Security Perspective

Luca Cassano; Stefano Di Mascio; Alessandro Palumbo; Alessandra Menicucci; Gianluca Furano; Giuseppe Bianchi; Marco Ottavi

doi:10.1109/DFT56152.2022.9962352

Is RISC-V ready for Space? A Security Perspective

Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi

Computer Architecture Design and Test for Embedded Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

185 Downloads (Pure)

Abstract

Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.

Original language	English
Title of host publication	Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022
Editors	Luca Cassano, Sreejit Chakravarty, Alberto Bosio
Publisher	IEEE
ISBN (Electronic)	978-1-6654-5938-9
DOIs	https://doi.org/10.1109/DFT56152.2022.9962352
Publication status	Published - 30 Nov 2022
Event	35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 - Austin, United States Duration: 19 Oct 2022 → 21 Oct 2022 Conference number: 35

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Volume	2022-October
ISSN (Print)	2576-1501
ISSN (Electronic)	2765-933X

Conference

Conference	35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022
Abbreviated title	DFT 2022
Country/Territory	United States
City	Austin
Period	19/10/22 → 21/10/22

Keywords

Hardware Security
Hardware Trojan Horses
Microarchitectural Side-Channel Attacks
Microprocessors
RISC-V
Space Applications.
2023 OA procedure

Access to Document

10.1109/DFT56152.2022.9962352

Is_RISC-V_ready_for_Space_A_Security_PerspectiveFinal published version, 200 KBLicence: Taverne

Cite this

Cassano, L., Mascio, S. D., Palumbo, A., Menicucci, A., Furano, G., Bianchi, G., & Ottavi, M. (2022). Is RISC-V ready for Space? A Security Perspective. In L. Cassano, S. Chakravarty, & A. Bosio (Eds.), Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October). IEEE. https://doi.org/10.1109/DFT56152.2022.9962352

Cassano, Luca ; Mascio, Stefano Di ; Palumbo, Alessandro et al. / Is RISC-V ready for Space? A Security Perspective. Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022. editor / Luca Cassano ; Sreejit Chakravarty ; Alberto Bosio. IEEE, 2022. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

@inproceedings{e21163d5e0344cc6ae5c5b459b1de06d,

title = "Is RISC-V ready for Space? A Security Perspective",

abstract = "Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.",

keywords = "Hardware Security, Hardware Trojan Horses, Microarchitectural Side-Channel Attacks, Microprocessors, RISC-V, Space Applications., 2023 OA procedure",

author = "Luca Cassano and Mascio, {Stefano Di} and Alessandro Palumbo and Alessandra Menicucci and Gianluca Furano and Giuseppe Bianchi and Marco Ottavi",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, DFT 2022 ; Conference date: 19-10-2022 Through 21-10-2022",

year = "2022",

month = nov,

day = "30",

doi = "10.1109/DFT56152.2022.9962352",

language = "English",

series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT",

publisher = "IEEE",

editor = "Luca Cassano and Sreejit Chakravarty and Alberto Bosio",

booktitle = "Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022",

address = "United States",

}

Cassano, L, Mascio, SD, Palumbo, A, Menicucci, A, Furano, G, Bianchi, G & Ottavi, M 2022, Is RISC-V ready for Space? A Security Perspective. in L Cassano, S Chakravarty & A Bosio (eds), Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, vol. 2022-October, IEEE, 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, Texas, United States, 19/10/22. https://doi.org/10.1109/DFT56152.2022.9962352

Is RISC-V ready for Space? A Security Perspective. / Cassano, Luca; Mascio, Stefano Di; Palumbo, Alessandro et al.
Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022. ed. / Luca Cassano; Sreejit Chakravarty; Alberto Bosio. IEEE, 2022. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Is RISC-V ready for Space? A Security Perspective

AU - Cassano, Luca

AU - Mascio, Stefano Di

AU - Palumbo, Alessandro

AU - Menicucci, Alessandra

AU - Furano, Gianluca

AU - Bianchi, Giuseppe

AU - Ottavi, Marco

N1 - Conference code: 35

PY - 2022/11/30

Y1 - 2022/11/30

N2 - Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.

AB - Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.

KW - Hardware Security

KW - Hardware Trojan Horses

KW - Microarchitectural Side-Channel Attacks

KW - Microprocessors

KW - RISC-V

KW - Space Applications.

KW - 2023 OA procedure

UR - http://www.scopus.com/inward/record.url?scp=85143770279&partnerID=8YFLogxK

U2 - 10.1109/DFT56152.2022.9962352

DO - 10.1109/DFT56152.2022.9962352

M3 - Conference contribution

AN - SCOPUS:85143770279

T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT

BT - Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022

A2 - Cassano, Luca

A2 - Chakravarty, Sreejit

A2 - Bosio, Alberto

PB - IEEE

T2 - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022

Y2 - 19 October 2022 through 21 October 2022

ER -

Cassano L, Mascio SD, Palumbo A, Menicucci A, Furano G, Bianchi G et al. Is RISC-V ready for Space? A Security Perspective. In Cassano L, Chakravarty S, Bosio A, editors, Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022. IEEE. 2022. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT56152.2022.9962352

Is RISC-V ready for Space? A Security Perspective

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this