Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch

R.C.H. van de Beek, Eric A.M. Klumperink, C.S. Vaucher, Bram Nauta

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    This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the Voltage Controlled Delay Line of the DLL [1]. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the middle of the Delay Line and proportional to the square root of the frequency multiplication factor of the structure. A circuit design technique, called Impedance Level Scaling, is presented that allows the designer to optimize the noise and mismatch behavior of a circuit independent of other specifications such as speed and linearity. Applying this technique on delay cell design yields a direct trade-off between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.
    Original languageUndefined
    Title of host publication13th ProRISC Workshop on Circuits, Systems and Signal Processing
    Place of PublicationUtrecht
    Number of pages5
    ISBN (Print)90-73461-33-2
    Publication statusPublished - Nov 2002
    Event13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002 - Veldhoven, Netherlands
    Duration: 28 Nov 200229 Nov 2002
    Conference number: 13

    Publication series

    PublisherSTW Technology Foundation


    Workshop13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002


    • EWI-14415
    • IR-67440
    • METIS-207349

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