This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the Voltage Controlled Delay Line of the DLL . An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the middle of the Delay Line and proportional to the square root of the frequency multiplication factor of the structure. A circuit design technique, called Impedance Level Scaling, is presented that allows the designer to optimize the noise and mismatch behavior of a circuit independent of other specifications such as speed and linearity. Applying this technique on delay cell design yields a direct trade-off between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.
|Title of host publication||13th ProRISC Workshop on Circuits, Systems and Signal Processing|
|Place of Publication||Utrecht|
|Number of pages||5|
|Publication status||Published - Nov 2002|
|Event||13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002 - Veldhoven, Netherlands|
Duration: 28 Nov 2002 → 29 Nov 2002
Conference number: 13
|Publisher||STW Technology Foundation|
|Workshop||13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002|
|Period||28/11/02 → 29/11/02|
van de Beek, R. C. H., Klumperink, E. A. M., Vaucher, C. S., & Nauta, B. (2002). Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch. In 13th ProRISC Workshop on Circuits, Systems and Signal Processing (pp. 190-194). Utrecht: STW.