Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch

R.C.H. van de Beek, Eric A.M. Klumperink, C.S. Vaucher, Bram Nauta

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

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Abstract

This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the Voltage Controlled Delay Line of the DLL [1]. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the middle of the Delay Line and proportional to the square root of the frequency multiplication factor of the structure. A circuit design technique, called Impedance Level Scaling, is presented that allows the designer to optimize the noise and mismatch behavior of a circuit independent of other specifications such as speed and linearity. Applying this technique on delay cell design yields a direct trade-off between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.
Original languageUndefined
Title of host publication13th ProRISC Workshop on Circuits, Systems and Signal Processing
Place of PublicationUtrecht
PublisherSTW
Pages190-194
Number of pages5
ISBN (Print)90-73461-33-2
Publication statusPublished - Nov 2002
Event13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002 - Veldhoven, Netherlands
Duration: 28 Nov 200229 Nov 2002
Conference number: 13

Publication series

Name
PublisherSTW Technology Foundation

Workshop

Workshop13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002
CountryNetherlands
CityVeldhoven
Period28/11/0229/11/02

Keywords

  • EWI-14415
  • IR-67440
  • METIS-207349

Cite this

van de Beek, R. C. H., Klumperink, E. A. M., Vaucher, C. S., & Nauta, B. (2002). Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch. In 13th ProRISC Workshop on Circuits, Systems and Signal Processing (pp. 190-194). Utrecht: STW.
van de Beek, R.C.H. ; Klumperink, Eric A.M. ; Vaucher, C.S. ; Nauta, Bram. / Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch. 13th ProRISC Workshop on Circuits, Systems and Signal Processing. Utrecht : STW, 2002. pp. 190-194
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title = "Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch",
abstract = "This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the Voltage Controlled Delay Line of the DLL [1]. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the middle of the Delay Line and proportional to the square root of the frequency multiplication factor of the structure. A circuit design technique, called Impedance Level Scaling, is presented that allows the designer to optimize the noise and mismatch behavior of a circuit independent of other specifications such as speed and linearity. Applying this technique on delay cell design yields a direct trade-off between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.",
keywords = "EWI-14415, IR-67440, METIS-207349",
author = "{van de Beek}, R.C.H. and Klumperink, {Eric A.M.} and C.S. Vaucher and Bram Nauta",
year = "2002",
month = "11",
language = "Undefined",
isbn = "90-73461-33-2",
publisher = "STW",
pages = "190--194",
booktitle = "13th ProRISC Workshop on Circuits, Systems and Signal Processing",

}

van de Beek, RCH, Klumperink, EAM, Vaucher, CS & Nauta, B 2002, Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch. in 13th ProRISC Workshop on Circuits, Systems and Signal Processing. STW, Utrecht, pp. 190-194, 13th Workshop on Circuits, Systems and Signal Processing, ProRISC 2002, Veldhoven, Netherlands, 28/11/02.

Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch. / van de Beek, R.C.H.; Klumperink, Eric A.M.; Vaucher, C.S.; Nauta, Bram.

13th ProRISC Workshop on Circuits, Systems and Signal Processing. Utrecht : STW, 2002. p. 190-194.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

TY - GEN

T1 - Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch

AU - van de Beek, R.C.H.

AU - Klumperink, Eric A.M.

AU - Vaucher, C.S.

AU - Nauta, Bram

PY - 2002/11

Y1 - 2002/11

N2 - This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the Voltage Controlled Delay Line of the DLL [1]. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the middle of the Delay Line and proportional to the square root of the frequency multiplication factor of the structure. A circuit design technique, called Impedance Level Scaling, is presented that allows the designer to optimize the noise and mismatch behavior of a circuit independent of other specifications such as speed and linearity. Applying this technique on delay cell design yields a direct trade-off between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.

AB - This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the Voltage Controlled Delay Line of the DLL [1]. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the middle of the Delay Line and proportional to the square root of the frequency multiplication factor of the structure. A circuit design technique, called Impedance Level Scaling, is presented that allows the designer to optimize the noise and mismatch behavior of a circuit independent of other specifications such as speed and linearity. Applying this technique on delay cell design yields a direct trade-off between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.

KW - EWI-14415

KW - IR-67440

KW - METIS-207349

M3 - Conference contribution

SN - 90-73461-33-2

SP - 190

EP - 194

BT - 13th ProRISC Workshop on Circuits, Systems and Signal Processing

PB - STW

CY - Utrecht

ER -

van de Beek RCH, Klumperink EAM, Vaucher CS, Nauta B. Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch. In 13th ProRISC Workshop on Circuits, Systems and Signal Processing. Utrecht: STW. 2002. p. 190-194