Jitter-Power minimization of digital frequency synthesis architectures

Eric A.M. Klumperink, R. Dutta, Z. Ru, Bram Nauta, X. Gao

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    3 Citations (Scopus)
    8 Downloads (Pure)

    Abstract

    Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture (“ring counter‿) over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years.
    Original languageEnglish
    Title of host publicationIEEE International Symposium on Circuits and Systems, ISCAS 2011
    Place of PublicationPiscataway
    PublisherIEEE
    Pages165-168
    Number of pages4
    ISBN (Print)978-1-4244-9472-9
    DOIs
    Publication statusPublished - 16 May 2011
    EventIEEE International Symposium on Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
    Duration: 15 May 201118 May 2011

    Conference

    ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2011
    Abbreviated titleISCAS
    CountryBrazil
    CityRio de Janeiro
    Period15/05/1118/05/11

    Keywords

    • METIS-278749
    • EWI-20409
    • IR-78017

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