Layout optimalisation for bipolar power transistors

A.J. Mouthaan, A.B. van der Scheer, H. Boezen, B.H. Krabbenborg, H.C. de Graaff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Original languageUndefined
    Title of host publicationProceedings of the 25th European Solid State Device Research Conference, ESSDERC '95
    Place of PublicationThe Netherlands Congress Centre, The Hague
    Publication statusPublished - 25 Sept 1995


    • METIS-113972

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