A new generation of highly dependable multi- processor Systems-on-Chip for safety-critical applications under harsh environments with zero down-time is emerging. In this paper1, the approach towards reaching this ultimate goal is explained. Crucial is this method is linking the measurement data of so-called (on-chip) health monitors during life time with the measurements of degrading key performance parameters of the cores involved. The focus will be here on processor cores, with delay as one of the most critical aging dependent parameters. An extensive (accelerated)-test program was set-up to evaluate the aging of both the health monitors as well as delay of an industrial reconfigurable processor core in harsh environments. The correlation between them will serve as the basis of real-time on- chip health-monitoring based prognostics for life-time prediction, enabling a zero down-time for safety-critical applications.
|Publisher||IEEE Computer Society|
|Conference||IEEE International Conference On Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Santorini, Greece|
|Period||1/05/14 → …|
- CAES-TDT: Testable Design and Test