The increasing amount of data produced in satellites
poses a downlink communication problem due to the limited data
rate of the downlink. This bottleneck is solved by introducing
more and more processing power on-board to compress data
to a satisfiable rate. Currently, this processing power is often
provided by custom off the shelf hardware which is needed to
run the complex image compression standards. The increase in
required processing power often increases the energy required to
power the hardware. This in turn pushes algorithm developers to
develop lower complexity algorithms which are able to compress
the data for the least amount of processing per data element.
On the other hand hardware developers are pushed to develop
flexible hardware which can be used on multiple missions to cut
development cost and can be re-used for different missions.
This paper introduces an algorithm which has been developed
to compress hyperspectral images at low complexity and
describes its mapping to a new hardware platform which has
been developed to offer flexibility as well as high performance
processing power called the Xentium tile processor.
|Publisher||IEEE Computer Society Press|
|Conference||NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009|
|Period||29/07/09 → 1/08/09|
|Other||29 July - 1 August 2009|