Low-Complexity Hyperspectral Image Compression on a Multi-tiled Architecture

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    The increasing amount of data produced in satellites poses a downlink communication problem due to the limited data rate of the downlink. This bottleneck is solved by introducing more and more processing power on-board to compress data to a satisfiable rate. Currently, this processing power is often provided by custom off the shelf hardware which is needed to run the complex image compression standards. The increase in required processing power often increases the energy required to power the hardware. This in turn pushes algorithm developers to develop lower complexity algorithms which are able to compress the data for the least amount of processing per data element. On the other hand hardware developers are pushed to develop flexible hardware which can be used on multiple missions to cut development cost and can be re-used for different missions. This paper introduces an algorithm which has been developed to compress hyperspectral images at low complexity and describes its mapping to a new hardware platform which has been developed to offer flexibility as well as high performance processing power called the Xentium tile processor.
    Original languageUndefined
    Title of host publicationProceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2009)
    Place of PublicationUnited State America
    PublisherIEEE Computer Society
    Number of pages6
    ISBN (Print)978-0-7695-3714-6
    Publication statusPublished - 29 Jul 2009

    Publication series

    PublisherIEEE Computer Society Press


    • IR-68665
    • METIS-264135
    • EWI-16476

    Cite this

    Walters, K. H. G., Kokkeler, A. B. J., Gerez, S. H., & Smit, G. J. M. (2009). Low-Complexity Hyperspectral Image Compression on a Multi-tiled Architecture. In Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2009) (pp. 330-335). United State America: IEEE Computer Society. https://doi.org/10.1109/AHS.2009.28