Low Cost & Fast Turnaround: Reconfigurable Graph-Based Execution Units

New devices with the efficiency of full-custom designs and the programmability of FPGAs will ease many aspects of the design of complex systems, without the high cost of mask production. The possibility of in-circuit programming and even dynamic reconfiguration offers great advantages over the traditional design approach. One instance of a fully programmable architecture which offers a platform for rapid prototyping, quick market and application evaluation, is introduced in the form of a field programmable function array (FPFA). The design of such a device is extremely challenging as the aspects of physical design for speed and low-power, the construction of an ALU which is optimal for as many applications as possible, as well as highly efficient mappings of algorithms, are extremely important for a successful device which suits many applications. This paper introduces the reader with the concept of reprogrammable devices with graph-based execution of arithmetic expressions, the corresponding principles of operation, the aspects of low-power operation of the proposed design, the corresponding physical design of the ALU, algorithmic mappings of systems on a chip and the performance aspects compared to other architectures and implementations.