Low-cost guaranteed-throughput communication ring for real-time streaming MPSoCs

B.H.J. Dekens, Philip Sebastian Kurtin, Marco Jan Gerrit Bekooij, Gerardus Johannes Maria Smit

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    8 Citations (Scopus)
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    Connection-oriented guaranteed-throughput mesh-based networks on chip have been proposed as a replacement for buses in real-time embedded multiprocessor systems such as software defined radios. Even with attractive features like throughput and latency guarantees they are not always used because their hardware cost tends to be higher than buses. In this paper we present a communication ring that provides throughput and latency guarantees. This ring is an attractive communication network as replacement for buses for small to medium scale embedded multiprocessor systems for real-time stream processing because of its relatively low hardware cost. We show that the data serialization of our ring makes it contention free and enables sharing of buffers which reduces the hardware cost. A further cost reduction is achieved by implementing end-to-end flow-control in software and by supporting only writes over the network. Data-flow analysis techniques are used to prove that throughput and latency guarantees can be given despite that the proposed communication ring is connectionless. We evaluated the performance and hardware cost of our communication ring using a 16 core multiprocessor system and a real-time PAL video decoder application. This design was implemented on a Virtex 6 FPGA and the ring was found to use roughly 2% of the logic cells used for the complete MPSoC design. Such a low hardware cost can justify the use of the ring in systems with low bandwidth utilization, as is the case for our PAL video decoder application which uses only 3% of the available bandwidth.
    Original languageUndefined
    Title of host publicationProceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing (DASIP)
    Place of PublicationLos Alamitos, CA, USA
    Number of pages8
    ISBN (Print)1966-7116
    Publication statusPublished - 8 Oct 2013
    Event2013 Conference on Design and Architectures for Signal and Image Processing, DASIP 2013 - Cagliari, Italy
    Duration: 8 Oct 201310 Oct 2013

    Publication series

    ISSN (Print)1966-7116


    Conference2013 Conference on Design and Architectures for Signal and Image Processing, DASIP 2013
    Abbreviated titleDASIP
    Internet address


    • EWI-23963
    • Topology
    • Packet Switching
    • Synchronous Data Flow
    • IR-87860
    • Network topology
    • Guaranteed Throughput
    • Hardware
    • METIS-300156
    • Throughput

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