Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs

B.H.J. Dekens, Philip Sebastian Kurtin, Gerardus Johannes Maria Smit, Marco Jan Gerrit Bekooij

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    2 Downloads (Pure)

    Abstract

    Connection-oriented Guaranteed-Throughput (GT) mesh-based Networks on Chip (NoCs) have been proposed as a replacement for buses in real-time stream processing systems but are currently rarely used as hardware cost tends to be higher than conventional interconnects. Recently an interconnect with a ring topology was introduced as a low-cost alternative for use in medium scale homogeneous Multiple Processor System on Chip (MPSoC) designs. Cost-effective integration of stream processing accelerators would require an extension of this ring interconnect. We present a dual-ring communication infrastructure for heterogeneous MPSoC designs. Data and credits are transferred between tiles using their separate, oppositely directed, rings. The minimum throughput is determined by analysis of a Cyclo-Static Data Flow (CSDF) model for a system with communication between accelerators and processors. The performance benefits and costs are evaluated by integration of our dual ring and an accelerator in a 16 core MPSoC which is mapped on a Virtex6 FPGA. On this MPSoC a real-time PAL video decoder is executed. A performance gain of a factor 3.6 was obtained at an increase in hardware cost of only 8.5%.
    Original languageUndefined
    Title of host publication2014 Conference on Design and Architectures for Signal and Image Processing (DASIP)
    Place of PublicationFrance
    PublisherECSI Media
    Pages157-164
    Number of pages8
    ISBN (Print)979-10-92279-06-1
    DOIs
    Publication statusPublished - 8 Oct 2014
    Event2014 Conference on Design and Architectures for Signal and Image Processing, DASIP 2014 - Madrid, Spain
    Duration: 8 Oct 201410 Oct 2014
    https://ecsi.org/dasip2014/proceedings

    Publication series

    Name
    PublisherECSI Media

    Conference

    Conference2014 Conference on Design and Architectures for Signal and Image Processing, DASIP 2014
    Abbreviated titleDASIP
    CountrySpain
    CityMadrid
    Period8/10/1410/10/14
    Internet address

    Keywords

    • Real time systems
    • interconnects
    • EWI-25173
    • METIS-309608
    • Accelerators
    • Hardware
    • Embedded Systems
    • IR-93329

    Cite this

    Dekens, B. H. J., Kurtin, P. S., Smit, G. J. M., & Bekooij, M. J. G. (2014). Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs. In 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP) (pp. 157-164). France: ECSI Media. https://doi.org/10.1109/DASIP.2014.7115628, https://doi.org/10.13140/2.1.1522.9765
    Dekens, B.H.J. ; Kurtin, Philip Sebastian ; Smit, Gerardus Johannes Maria ; Bekooij, Marco Jan Gerrit. / Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). France : ECSI Media, 2014. pp. 157-164
    @inproceedings{3a930c78cf874b7b99b1d20f55aa2e88,
    title = "Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs",
    abstract = "Connection-oriented Guaranteed-Throughput (GT) mesh-based Networks on Chip (NoCs) have been proposed as a replacement for buses in real-time stream processing systems but are currently rarely used as hardware cost tends to be higher than conventional interconnects. Recently an interconnect with a ring topology was introduced as a low-cost alternative for use in medium scale homogeneous Multiple Processor System on Chip (MPSoC) designs. Cost-effective integration of stream processing accelerators would require an extension of this ring interconnect. We present a dual-ring communication infrastructure for heterogeneous MPSoC designs. Data and credits are transferred between tiles using their separate, oppositely directed, rings. The minimum throughput is determined by analysis of a Cyclo-Static Data Flow (CSDF) model for a system with communication between accelerators and processors. The performance benefits and costs are evaluated by integration of our dual ring and an accelerator in a 16 core MPSoC which is mapped on a Virtex6 FPGA. On this MPSoC a real-time PAL video decoder is executed. A performance gain of a factor 3.6 was obtained at an increase in hardware cost of only 8.5{\%}.",
    keywords = "Real time systems, interconnects, EWI-25173, METIS-309608, Accelerators, Hardware, Embedded Systems, IR-93329",
    author = "B.H.J. Dekens and Kurtin, {Philip Sebastian} and Smit, {Gerardus Johannes Maria} and Bekooij, {Marco Jan Gerrit}",
    note = "http://dx.doi.org/10.13140/2.1.1522.9765",
    year = "2014",
    month = "10",
    day = "8",
    doi = "10.1109/DASIP.2014.7115628",
    language = "Undefined",
    isbn = "979-10-92279-06-1",
    publisher = "ECSI Media",
    pages = "157--164",
    booktitle = "2014 Conference on Design and Architectures for Signal and Image Processing (DASIP)",

    }

    Dekens, BHJ, Kurtin, PS, Smit, GJM & Bekooij, MJG 2014, Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs. in 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). ECSI Media, France, pp. 157-164, 2014 Conference on Design and Architectures for Signal and Image Processing, DASIP 2014, Madrid, Spain, 8/10/14. https://doi.org/10.1109/DASIP.2014.7115628, https://doi.org/10.13140/2.1.1522.9765

    Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs. / Dekens, B.H.J.; Kurtin, Philip Sebastian; Smit, Gerardus Johannes Maria; Bekooij, Marco Jan Gerrit.

    2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). France : ECSI Media, 2014. p. 157-164.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    TY - GEN

    T1 - Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs

    AU - Dekens, B.H.J.

    AU - Kurtin, Philip Sebastian

    AU - Smit, Gerardus Johannes Maria

    AU - Bekooij, Marco Jan Gerrit

    N1 - http://dx.doi.org/10.13140/2.1.1522.9765

    PY - 2014/10/8

    Y1 - 2014/10/8

    N2 - Connection-oriented Guaranteed-Throughput (GT) mesh-based Networks on Chip (NoCs) have been proposed as a replacement for buses in real-time stream processing systems but are currently rarely used as hardware cost tends to be higher than conventional interconnects. Recently an interconnect with a ring topology was introduced as a low-cost alternative for use in medium scale homogeneous Multiple Processor System on Chip (MPSoC) designs. Cost-effective integration of stream processing accelerators would require an extension of this ring interconnect. We present a dual-ring communication infrastructure for heterogeneous MPSoC designs. Data and credits are transferred between tiles using their separate, oppositely directed, rings. The minimum throughput is determined by analysis of a Cyclo-Static Data Flow (CSDF) model for a system with communication between accelerators and processors. The performance benefits and costs are evaluated by integration of our dual ring and an accelerator in a 16 core MPSoC which is mapped on a Virtex6 FPGA. On this MPSoC a real-time PAL video decoder is executed. A performance gain of a factor 3.6 was obtained at an increase in hardware cost of only 8.5%.

    AB - Connection-oriented Guaranteed-Throughput (GT) mesh-based Networks on Chip (NoCs) have been proposed as a replacement for buses in real-time stream processing systems but are currently rarely used as hardware cost tends to be higher than conventional interconnects. Recently an interconnect with a ring topology was introduced as a low-cost alternative for use in medium scale homogeneous Multiple Processor System on Chip (MPSoC) designs. Cost-effective integration of stream processing accelerators would require an extension of this ring interconnect. We present a dual-ring communication infrastructure for heterogeneous MPSoC designs. Data and credits are transferred between tiles using their separate, oppositely directed, rings. The minimum throughput is determined by analysis of a Cyclo-Static Data Flow (CSDF) model for a system with communication between accelerators and processors. The performance benefits and costs are evaluated by integration of our dual ring and an accelerator in a 16 core MPSoC which is mapped on a Virtex6 FPGA. On this MPSoC a real-time PAL video decoder is executed. A performance gain of a factor 3.6 was obtained at an increase in hardware cost of only 8.5%.

    KW - Real time systems

    KW - interconnects

    KW - EWI-25173

    KW - METIS-309608

    KW - Accelerators

    KW - Hardware

    KW - Embedded Systems

    KW - IR-93329

    U2 - 10.1109/DASIP.2014.7115628

    DO - 10.1109/DASIP.2014.7115628

    M3 - Conference contribution

    SN - 979-10-92279-06-1

    SP - 157

    EP - 164

    BT - 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP)

    PB - ECSI Media

    CY - France

    ER -

    Dekens BHJ, Kurtin PS, Smit GJM, Bekooij MJG. Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs. In 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). France: ECSI Media. 2014. p. 157-164 https://doi.org/10.1109/DASIP.2014.7115628, https://doi.org/10.13140/2.1.1522.9765