TY - JOUR
T1 - Low cost memristor associative memory design for full and partial matching applications
AU - Yang, Y.
AU - Mathew, J.
AU - Chakraborty, R.S.
AU - Ottavi, M.
AU - Pradhan, D.K.
PY - 2016
Y1 - 2016
N2 - Novel memory circuits based on variable-resistance devices (such as memristors) have been recently proposed to overcome the limitations of CMOS based memories. These novel memories although based on different technologies, all share the principle of storing information as the resistance value imposed to a variable-resistance devices. Another promising application of memristors is in content-addressable memory (CAM). The study of memristor based CAM design has become increasingly important with the advent of new hybrid CMOS molecular technologies. To this end, we present a two-transistor-memristor (2T2M) bitcell for CAM design, suitable for low-power applications. The proposed circuit consists of memristors to store data and transistors as access devices, and utilizes complementary logic values at the input. We present detailed simulation based characterization (for both full match and partial match cases) and analysis, considering different word sizes of the proposed bitcells, including full parasitics, using BPTM 45-nm CMOS device models.
AB - Novel memory circuits based on variable-resistance devices (such as memristors) have been recently proposed to overcome the limitations of CMOS based memories. These novel memories although based on different technologies, all share the principle of storing information as the resistance value imposed to a variable-resistance devices. Another promising application of memristors is in content-addressable memory (CAM). The study of memristor based CAM design has become increasingly important with the advent of new hybrid CMOS molecular technologies. To this end, we present a two-transistor-memristor (2T2M) bitcell for CAM design, suitable for low-power applications. The proposed circuit consists of memristors to store data and transistors as access devices, and utilizes complementary logic values at the input. We present detailed simulation based characterization (for both full match and partial match cases) and analysis, considering different word sizes of the proposed bitcells, including full parasitics, using BPTM 45-nm CMOS device models.
UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-84969731173&partnerID=MN8TOARS
U2 - 10.1109/TNANO.2016.2553438
DO - 10.1109/TNANO.2016.2553438
M3 - Article
SN - 1536-125X
VL - 15
SP - 527
EP - 538
JO - IEEE transactions on nanotechnology
JF - IEEE transactions on nanotechnology
IS - 3
ER -