Low Energy Design Techniques For Data Converters

Research output: ThesisPhD Thesis - Research UT, graduation UTAcademic

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Abstract

Analog to Digital Converters (ADCs) are crucial to capture data in almost any Internet of Everything (IoE) device as sensed physical signals have to be converted into digital data, before some processing and data transmission can take place. Today, ADCs are designed for low supply energy consumption, usually expressed in energy-per-conversion step which for state-of-the art architecture is (stagnated) ~ 1fJ/conversion-step. However, the energy consumed from the always ON sensor interface circuitry e.g. the input driver is usually not taken into account and seldom addressed. This input drive energy (usually larger than the ADC supply energy) presents a major challenge in minimizing the energy consumption of e.g. autonomous and event-driven IoE applications. This thesis presents design techniques to reduce the amount of energy required to perform various operations during data conversion, such as comparison, buffering the input signal and sampling the buffered input signal. These techniques aim at reducing the amount of charge (and energy) required to perform each of these operations that require a certain capacitance to satisfy the theoretical kT/C noise limit for a given SNR. The energy consumption for charging-discharging of this capacitor is reduced by minimizing the voltage change across this capacitor for the operations mentioned above without compromising the SNR. The low energy design techniques presented in this thesis contributed towards attaining the lowest reported Walden FoM of 0.35 fJ/conv-step for the standalone SAR ADC. When including the energy consumption of the buffers the Walden FoM of 87 fJ/conv-step (using only a single supply voltage) is also the lowest among all the reported buffered SAR ADCs to the best of my knowledge. In addition the design techniques presented in this thesis allow the buffered SAR ADC to operate from a single supply voltage (1.2 V) thereby alleviating the need of any additional supply voltage level to interface with wireless sensor nodes.
Original languageEnglish
QualificationDoctor of Philosophy
Awarding Institution
  • University of Twente
Supervisors/Advisors
  • Nauta, Bram , Supervisor
  • Annema, Anne J., Co-Supervisor
Award date13 Nov 2019
Place of PublicationEnschede
Publisher
Print ISBNs978-90-365-4869-4
DOIs
Publication statusPublished - 13 Nov 2019

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Digital to analog conversion
Energy utilization
Electric potential
Capacitors
Internet
Sensor nodes
Data communication systems
Data acquisition
Capacitance
Sampling
Sensors
Processing

Keywords

  • ADC
  • SAR ADC
  • Figure of merit
  • Sampling
  • Energy efficient
  • Noise
  • comparators (circuits)
  • INL
  • DNL
  • Class-A driver
  • input buffer
  • SNR
  • SFDR
  • SNDR
  • THD
  • quenching

Cite this

Bindra, Harijot Singh. / Low Energy Design Techniques For Data Converters. Enschede : University of Twente, 2019. 163 p.
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abstract = "Analog to Digital Converters (ADCs) are crucial to capture data in almost any Internet of Everything (IoE) device as sensed physical signals have to be converted into digital data, before some processing and data transmission can take place. Today, ADCs are designed for low supply energy consumption, usually expressed in energy-per-conversion step which for state-of-the art architecture is (stagnated) ~ 1fJ/conversion-step. However, the energy consumed from the always ON sensor interface circuitry e.g. the input driver is usually not taken into account and seldom addressed. This input drive energy (usually larger than the ADC supply energy) presents a major challenge in minimizing the energy consumption of e.g. autonomous and event-driven IoE applications. This thesis presents design techniques to reduce the amount of energy required to perform various operations during data conversion, such as comparison, buffering the input signal and sampling the buffered input signal. These techniques aim at reducing the amount of charge (and energy) required to perform each of these operations that require a certain capacitance to satisfy the theoretical kT/C noise limit for a given SNR. The energy consumption for charging-discharging of this capacitor is reduced by minimizing the voltage change across this capacitor for the operations mentioned above without compromising the SNR. The low energy design techniques presented in this thesis contributed towards attaining the lowest reported Walden FoM of 0.35 fJ/conv-step for the standalone SAR ADC. When including the energy consumption of the buffers the Walden FoM of 87 fJ/conv-step (using only a single supply voltage) is also the lowest among all the reported buffered SAR ADCs to the best of my knowledge. In addition the design techniques presented in this thesis allow the buffered SAR ADC to operate from a single supply voltage (1.2 V) thereby alleviating the need of any additional supply voltage level to interface with wireless sensor nodes.",
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year = "2019",
month = "11",
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doi = "10.3990/1.9789036548694",
language = "English",
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Bindra, HS 2019, 'Low Energy Design Techniques For Data Converters', Doctor of Philosophy, University of Twente, Enschede. https://doi.org/10.3990/1.9789036548694

Low Energy Design Techniques For Data Converters. / Bindra, Harijot Singh.

Enschede : University of Twente, 2019. 163 p.

Research output: ThesisPhD Thesis - Research UT, graduation UTAcademic

TY - THES

T1 - Low Energy Design Techniques For Data Converters

AU - Bindra, Harijot Singh

PY - 2019/11/13

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N2 - Analog to Digital Converters (ADCs) are crucial to capture data in almost any Internet of Everything (IoE) device as sensed physical signals have to be converted into digital data, before some processing and data transmission can take place. Today, ADCs are designed for low supply energy consumption, usually expressed in energy-per-conversion step which for state-of-the art architecture is (stagnated) ~ 1fJ/conversion-step. However, the energy consumed from the always ON sensor interface circuitry e.g. the input driver is usually not taken into account and seldom addressed. This input drive energy (usually larger than the ADC supply energy) presents a major challenge in minimizing the energy consumption of e.g. autonomous and event-driven IoE applications. This thesis presents design techniques to reduce the amount of energy required to perform various operations during data conversion, such as comparison, buffering the input signal and sampling the buffered input signal. These techniques aim at reducing the amount of charge (and energy) required to perform each of these operations that require a certain capacitance to satisfy the theoretical kT/C noise limit for a given SNR. The energy consumption for charging-discharging of this capacitor is reduced by minimizing the voltage change across this capacitor for the operations mentioned above without compromising the SNR. The low energy design techniques presented in this thesis contributed towards attaining the lowest reported Walden FoM of 0.35 fJ/conv-step for the standalone SAR ADC. When including the energy consumption of the buffers the Walden FoM of 87 fJ/conv-step (using only a single supply voltage) is also the lowest among all the reported buffered SAR ADCs to the best of my knowledge. In addition the design techniques presented in this thesis allow the buffered SAR ADC to operate from a single supply voltage (1.2 V) thereby alleviating the need of any additional supply voltage level to interface with wireless sensor nodes.

AB - Analog to Digital Converters (ADCs) are crucial to capture data in almost any Internet of Everything (IoE) device as sensed physical signals have to be converted into digital data, before some processing and data transmission can take place. Today, ADCs are designed for low supply energy consumption, usually expressed in energy-per-conversion step which for state-of-the art architecture is (stagnated) ~ 1fJ/conversion-step. However, the energy consumed from the always ON sensor interface circuitry e.g. the input driver is usually not taken into account and seldom addressed. This input drive energy (usually larger than the ADC supply energy) presents a major challenge in minimizing the energy consumption of e.g. autonomous and event-driven IoE applications. This thesis presents design techniques to reduce the amount of energy required to perform various operations during data conversion, such as comparison, buffering the input signal and sampling the buffered input signal. These techniques aim at reducing the amount of charge (and energy) required to perform each of these operations that require a certain capacitance to satisfy the theoretical kT/C noise limit for a given SNR. The energy consumption for charging-discharging of this capacitor is reduced by minimizing the voltage change across this capacitor for the operations mentioned above without compromising the SNR. The low energy design techniques presented in this thesis contributed towards attaining the lowest reported Walden FoM of 0.35 fJ/conv-step for the standalone SAR ADC. When including the energy consumption of the buffers the Walden FoM of 87 fJ/conv-step (using only a single supply voltage) is also the lowest among all the reported buffered SAR ADCs to the best of my knowledge. In addition the design techniques presented in this thesis allow the buffered SAR ADC to operate from a single supply voltage (1.2 V) thereby alleviating the need of any additional supply voltage level to interface with wireless sensor nodes.

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KW - SAR ADC

KW - Figure of merit

KW - Sampling

KW - Energy efficient

KW - Noise

KW - comparators (circuits)

KW - INL

KW - DNL

KW - Class-A driver

KW - input buffer

KW - SNR

KW - SFDR

KW - SNDR

KW - THD

KW - quenching

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DO - 10.3990/1.9789036548694

M3 - PhD Thesis - Research UT, graduation UT

SN - 978-90-365-4869-4

PB - University of Twente

CY - Enschede

ER -