Low Energy Design Techniques For Data Converters

Harijot Singh Bindra

Research output: Thesis › PhD Thesis - Research UT, graduation UT

2010 Downloads (Pure)

5 Conference contribution
1 Article

6 results

2019
A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator
Bindra, H. S., Annema, A.-J., Louwsma, S. M. & Nauta, B., 11 Jun 2019, 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers: Digest of Technical Papers. Piscataway, NJ: IEEE, p. C74-C75 8778093. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; vol. 2019).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Open Access
File
16 Citations (Scopus)

421 Downloads (Pure)
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply
Bindra, H. S., Annema, A. J., Wienk, G. J. M., Nauta, B. & Louwsma, S., 17 Apr 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC) . Austin, TX, USA: IEEE, 8780150. (Proceedings of the Custom Integrated Circuits Conference; vol. 2019-April).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Open Access
File
21 Citations (Scopus)

515 Downloads (Pure)
2018
A 1.2-V Dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise
Bindra, H. S. (Corresponding Author), Lokin, C. E., Schinkel, D., Annema, A. J. & Nauta, B., 1 Jul 2018, In: IEEE journal of solid-state circuits. 53, 7, p. 1902-1912 11 p.
Research output: Contribution to journal › Article › Academic › peer-review

Open Access
File
150 Citations (Scopus)

6636 Downloads (Pure)
2017
A 30fJ/comparison dynamic bias comparator
Bindra, H. S., Lokin, C. E., Annema, A. J. & Nauta, B., 12 Sept 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference . Leuven, Belgium: IEEE, p. 71-74 4 p.
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Open Access
File
42 Citations (Scopus)

1731 Downloads (Pure)
An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC
Bindra, H. S., Annema, A. J., Louwsma, S. M., van Tuijl, A. J. M. & Nauta, B., 13 Sept 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference. Leuven, Belgium: IEEE, p. 235 238 p.
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
15 Downloads (Pure)
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs
Bindra, H. S., Lechevallier, J. B., Annema, A. J., Louwsma, S. M., van Tuijl, A. J. M. & Nauta, B., 8 Nov 2017, IEEE Asian Solid-State Circuits Conference (A-SSCC): proceedings of technical papers. Piscataway, NJ: IEEE, p. 217-220 4 p.
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Open Access
File
7 Citations (Scopus)

344 Downloads (Pure)

Low Energy Design Techniques For Data Converters

Research output

Search results

A 0.2 - 8 MS/s 10b flexible SAR ADC Achieving 0.35 - 2.5 fJ/Conv-Step and using self-quenched dynamic bias comparator

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

A 1.2-V Dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise

A 30fJ/comparison dynamic bias comparator

An Energy reduced sampling technique applied to 10b 1MS/s SAR ADC

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs