Low Energy Design Techniques For Data Converters

Harijot Singh Bindra

Research output: Thesis › PhD Thesis - Research UT, graduation UT

2012 Downloads (Pure)

5 Conference contribution
1 Article

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2018
A 1.2-V Dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise
Bindra, H. S. (Corresponding Author), Lokin, C. E., Schinkel, D., Annema, A. J. & Nauta, B., 1 Jul 2018, In: IEEE journal of solid-state circuits. 53, 7, p. 1902-1912 11 p.
Research output: Contribution to journal › Article › Academic › peer-review

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151 Citations (Scopus)

6648 Downloads (Pure)