Low-Jitter Clock Multiplication: a Comparison between PLLs and DLLs

R.C.H. van de Beek, Eric A.M. Klumperink, Cicero S. Vaucher, Bram Nauta

    Research output: Contribution to journalArticleAcademicpeer-review

    48 Citations (Scopus)
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    Abstract

    This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage.
    Original languageEnglish
    Pages (from-to)555-566
    Number of pages12
    JournalIEEE transactions on circuits and systems II: analog and digital signal processing
    Volume49
    Issue number8
    DOIs
    Publication statusPublished - Aug 2002

    Keywords

    • Frequency conversion
    • Jitter
    • phase-locked loops (PLLs)
    • Circuit modeling
    • EWI-14402
    • METIS-205870
    • IR-43094
    • delay-locked loops (DLLs)

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