Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

X. Gao; Eric A.M. Klumperink; Bram Nauta

doi:10.1109/ISCAS.2007.378767

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

X. Gao, Eric A.M. Klumperink, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

6 Citations (Scopus)

304 Downloads (Pure)

Abstract

Abstract—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.

Original language	English
Title of host publication	Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)
Place of Publication	Piscataway
Publisher	IEEE
Pages	2854-2857
Number of pages	4
ISBN (Print)	1-4244-0921-7
DOIs	https://doi.org/10.1109/ISCAS.2007.378767
Publication status	Published - 30 May 2007
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, United States Duration: 27 May 2007 → 30 May 2007 http://www.iscas2007.org/

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2007
Abbreviated title	ISCAS 2007
Country/Territory	United States
City	New Orleans
Period	27/05/07 → 30/05/07
Internet address	http://www.iscas2007.org/

Keywords

EWI-10893
IR-58147
METIS-241846

Access to Document

10.1109/ISCAS.2007.378767

low-jitter_multi-phaseFinal published version, 334 KB

Cite this

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title = "Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers",

abstract = "Abstract—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.",

keywords = "EWI-10893, IR-58147, METIS-241846",

author = "X. Gao and Klumperink, {Eric A.M.} and Bram Nauta",

note = "10.1109/ISCAS.2007.378767 ; IEEE International Symposium on Circuits and Systems, ISCAS 2007, ISCAS 2007 ; Conference date: 27-05-2007 Through 30-05-2007",

year = "2007",

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doi = "10.1109/ISCAS.2007.378767",

language = "English",

isbn = "1-4244-0921-7",

pages = "2854--2857",

booktitle = "Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)",

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Gao, X, Klumperink, EAM & Nauta, B 2007, Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. in Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007). IEEE, Piscataway, pp. 2854-2857, IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, Louisiana, United States, 27/05/07. https://doi.org/10.1109/ISCAS.2007.378767

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. / Gao, X.; Klumperink, Eric A.M.; Nauta, Bram.
Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007). Piscataway: IEEE, 2007. p. 2854-2857.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

AU - Gao, X.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

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PY - 2007/5/30

Y1 - 2007/5/30

N2 - Abstract—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.

AB - Abstract—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.

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KW - IR-58147

KW - METIS-241846

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M3 - Conference contribution

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BT - Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

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CY - Piscataway

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2007

Y2 - 27 May 2007 through 30 May 2007

ER -

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

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Keywords

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