Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

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    Abstract

    Abstract—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.
    Original languageEnglish
    Title of host publicationProceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)
    Place of PublicationPiscataway
    PublisherIEEE Computer Society Press
    Pages2854-2857
    Number of pages4
    ISBN (Print)1-4244-0921-7
    DOIs
    Publication statusPublished - 30 May 2007
    EventIEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, United States
    Duration: 27 May 200730 May 2007
    http://www.iscas2007.org/

    Conference

    ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2007
    Abbreviated titleISCAS 2007
    CountryUnited States
    CityNew Orleans
    Period27/05/0730/05/07
    Internet address

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    Keywords

    • EWI-10893
    • IR-58147
    • METIS-241846

    Cite this

    Gao, X., Klumperink, E. A. M., & Nauta, B. (2007). Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. In Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007) (pp. 2854-2857). Piscataway: IEEE Computer Society Press. https://doi.org/10.1109/ISCAS.2007.378767