Low power and low spur sampling PLL

X. Gao (Inventor), Ahmad Bahai (Inventor), Mounhir Bohsali (Inventor), Ali Djabbari (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), Gerard Socci (Inventor)

    Research output: Patent

    16 Downloads (Pure)

    Abstract

    Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.
    Original languageUndefined
    Patent numberUS8395427 B1
    Priority date20/12/10
    Publication statusPublished - 12 Mar 2013

    Keywords

    • METIS-297736
    • IR-86690
    • EWI-23522

    Cite this

    Gao, X., Bahai, A., Bohsali, M., Djabbari, A., Klumperink, E. A. M., Nauta, B., & Socci, G. (2013). Low power and low spur sampling PLL. (Patent No. US8395427 B1).
    Gao, X. (Inventor) ; Bahai, Ahmad (Inventor) ; Bohsali, Mounhir (Inventor) ; Djabbari, Ali (Inventor) ; Klumperink, Eric A.M. (Inventor) ; Nauta, Bram (Inventor) ; Socci, Gerard (Inventor). / Low power and low spur sampling PLL. Patent No.: US8395427 B1.
    @misc{6f08e7d111054989b29f2d4f67c41a2e,
    title = "Low power and low spur sampling PLL",
    abstract = "Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.",
    keywords = "METIS-297736, IR-86690, EWI-23522",
    author = "X. Gao and Ahmad Bahai and Mounhir Bohsali and Ali Djabbari and Klumperink, {Eric A.M.} and Bram Nauta and Gerard Socci",
    year = "2013",
    month = "3",
    day = "12",
    language = "Undefined",
    type = "Patent",
    note = "US8395427 B1",

    }

    Gao, X, Bahai, A, Bohsali, M, Djabbari, A, Klumperink, EAM, Nauta, B & Socci, G 2013, Low power and low spur sampling PLL, Patent No. US8395427 B1.

    Low power and low spur sampling PLL. / Gao, X. (Inventor); Bahai, Ahmad (Inventor); Bohsali, Mounhir (Inventor); Djabbari, Ali (Inventor); Klumperink, Eric A.M. (Inventor); Nauta, Bram (Inventor); Socci, Gerard (Inventor).

    Patent No.: US8395427 B1.

    Research output: Patent

    TY - PAT

    T1 - Low power and low spur sampling PLL

    AU - Gao, X.

    AU - Bahai, Ahmad

    AU - Bohsali, Mounhir

    AU - Djabbari, Ali

    AU - Klumperink, Eric A.M.

    AU - Nauta, Bram

    AU - Socci, Gerard

    PY - 2013/3/12

    Y1 - 2013/3/12

    N2 - Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

    AB - Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

    KW - METIS-297736

    KW - IR-86690

    KW - EWI-23522

    M3 - Patent

    M1 - US8395427 B1

    ER -

    Gao X, Bahai A, Bohsali M, Djabbari A, Klumperink EAM, Nauta B et al, inventors. Low power and low spur sampling PLL. US8395427 B1. 2013 Mar 12.