Low power and low spur sampling PLL

X. Gao (Inventor), Ahmad Bahai (Inventor), Mounhir Bohsali (Inventor), Ali Djabbari (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), Gerard Socci (Inventor)

    Research output: Patent

    21 Downloads (Pure)

    Abstract

    Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.
    Original languageUndefined
    Patent numberUS8395427 B1
    Priority date20/12/10
    Publication statusPublished - 12 Mar 2013

    Keywords

    • METIS-297736
    • IR-86690
    • EWI-23522

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