Low power and low spur sampling PLL

X. Gao (Inventor), Eric A.M. Klumperink (Inventor), A. Bahai (Inventor), M. Bohsali (Inventor), Bram Nauta (Inventor), A. Djabbari (Inventor), G. Socci (Inventor)

    Research output: Patent

    Abstract

    Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.
    Original languageUndefined
    Patent numberUS2013038365 A1
    Priority date20/12/10
    Publication statusPublished - 20 Dec 2010

    Keywords

    • METIS-276780
    • EWI-20184

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