Low power and low spur sampling PLL

X. Gao; Eric A.M. Klumperink; A. Bahai; M. Bohsali; Bram Nauta; A. Djabbari; G. Socci

Low power and low spur sampling PLL

X. Gao (Inventor)
, Eric A.M. Klumperink (Inventor)
, A. Bahai (Inventor)
, M. Bohsali (Inventor)
, Bram Nauta (Inventor)
, A. Djabbari (Inventor)
, G. Socci (Inventor)

Research output: Patent

Abstract

Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

Original language	Undefined
Patent number	US2013038365 A1
Priority date	20/12/10
Publication status	Published - 20 Dec 2010

Keywords

METIS-276780
EWI-20184

Cite this

@misc{944ea60e3c0049ae93a42fd56e87e598,

title = "Low power and low spur sampling PLL",

abstract = "Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.",

keywords = "METIS-276780, EWI-20184",

author = "X. Gao and Klumperink, \{Eric A.M.\} and A. Bahai and M. Bohsali and Bram Nauta and A. Djabbari and G. Socci",

year = "2010",

month = dec,

day = "20",

language = "Undefined",

type = "Patent",

note = "US2013038365 A1",

}

TY - PAT

T1 - Low power and low spur sampling PLL

AU - Gao, X.

AU - Klumperink, Eric A.M.

AU - Bahai, A.

AU - Bohsali, M.

AU - Nauta, Bram

AU - Djabbari, A.

AU - Socci, G.

PY - 2010/12/20

Y1 - 2010/12/20

N2 - Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

AB - Abstract Control circuitry and method of controlling a sampling phase locked loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

KW - METIS-276780

KW - EWI-20184

UR - https://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=8395427B1&KC=B1&FT=D&ND=4&date=20130312&DB=worldwide.espacenet.com&locale=en_EP#

M3 - Patent

M1 - US2013038365 A1

ER -

Low power and low spur sampling PLL

Abstract

Keywords

Other files and links

Research output

Low power and low spur sampling PLL

Cite this