Low-Power High-Linearity Mixer-First receiver using implicit capacitive Stacking with 3× voltage gain

Vijaya Kumar Purushothaman*, Eric A.M. Klumperink, Roel Plompen, Bram Nauta

*Corresponding author for this work

Research output: Contribution to journalArticleAcademicpeer-review

23 Citations (Scopus)
427 Downloads (Pure)

Abstract

In this article, we present a passive mixer-first receiver front end providing a low-power integrated solution for high interference robustness in radios targeting Internet-of-Things (IoT) applications. The receiver front end employs a novel N-path filter/mixer, a linear baseband amplifier, and a step-up transformer to realize sub-6-dB NF and >20-dBm OB-IIP3 concurrently. The proposed N-path filter/mixer exploits an implicit capacitive stacking principle to achieve passive voltage gain of 3 during down-conversion and high out-of-band linearity simultaneously while using at least 2x less total capacitance for the same RF bandwidth compared to a conventional switch-capacitor N-path filter. Fabricated in 22-nm complementary metal-oxide-semiconductor (CMOS) fully depleted silicon on insulator (FDSOI), the receiver prototype--including a 2:6 transformer--occupies only 0.2 mm² of active area. Operating in the frequency range of 1.8-2.8 GHz, the front end provides a 45-47-dB conversion gain and a baseband bandwidth of 2 MHz. Due to passive voltage gain in the filter/mixer and transformer, the implemented front end consumes only 1.7-2.5 mW of power to achieve <6-dB NF, ~24/60/1 dBm out-of-band IIP3/IIP2/B1dB, respectively.

Original languageEnglish
Pages (from-to)245-259
Number of pages15
JournalIEEE journal of solid-state circuits
Volume57
Issue number1
Early online date7 Jul 2021
DOIs
Publication statusPublished - 1 Jan 2022

Keywords

  • passive mixer
  • N-path filter
  • CMOS
  • mixer-first receiver
  • Bottom-plate mixing
  • capacitive stacking
  • high linearity
  • Low Power
  • low Noice
  • interference-robust
  • FDSOI
  • transformer

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