Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Daniel Schinkel, E. Mensink, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

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    67 Citations (Scopus)
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    Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.
    Original languageEnglish
    Pages (from-to)12-21
    Number of pages10
    JournalIEEE transactions on very large scale integration (VLSI) systems
    Issue number1
    Publication statusPublished - Jan 2009


    • METIS-263775
    • EWI-15220
    • IR-65427


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