Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

M.A.T. Sanduleanu, Bram Nauta, Hans Wallinga

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    Abstract

    This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW.
    Original languageEnglish
    Title of host publicationESSCIRC '97: proceedings of the 23rd European Solid-State Circuits Conference, 1997
    Place of PublicationPiscataway, NJ, USA
    PublisherIEEE
    Pages204-207
    Publication statusPublished - 26 Jan 1997
    Event23rd European Solid-State Circuits Conference, ESSCIRC 1997 - Southampton, United Kingdom
    Duration: 16 Sep 199718 Sep 1997
    Conference number: 23

    Publication series

    Name
    PublisherIEEE

    Conference

    Conference23rd European Solid-State Circuits Conference, ESSCIRC 1997
    Abbreviated titleESSCIRC
    CountryUnited Kingdom
    CitySouthampton
    Period16/09/9718/09/97

    Keywords

    • METIS-112856
    • IR-15974

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