Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

M.A.T. Sanduleanu; Bram Nauta; Hans Wallinga

Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

M.A.T. Sanduleanu
, Bram Nauta
, Hans Wallinga

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW.

Original language	English
Title of host publication	ESSCIRC '97: proceedings of the 23rd European Solid-State Circuits Conference, 1997
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	204-207
Publication status	Published - 26 Jan 1997
Event	23rd European Solid-State Circuits Conference, ESSCIRC 1997 - Southampton, United Kingdom Duration: 16 Sept 1997 → 18 Sept 1997 Conference number: 23

Publication series

Name
Publisher	IEEE

Conference

Conference	23rd European Solid-State Circuits Conference, ESSCIRC 1997
Abbreviated title	ESSCIRC
Country/Territory	United Kingdom
City	Southampton
Period	16/09/97 → 18/09/97

Keywords

METIS-112856
IR-15974

Access to Document

01470899

http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1470899

Cite this

@inproceedings{956800e98c784df7b7d5884b28fe790c,

title = "Low-power low-voltage chopped transconductance amplifier for noise and offset reduction",

abstract = "This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW.",

keywords = "METIS-112856, IR-15974",

author = "M.A.T. Sanduleanu and Bram Nauta and Hans Wallinga",

year = "1997",

month = jan,

day = "26",

language = "English",

publisher = "IEEE",

pages = "204--207",

booktitle = "ESSCIRC '97: proceedings of the 23rd European Solid-State Circuits Conference, 1997",

address = "United States",

note = "23rd European Solid-State Circuits Conference, ESSCIRC 1997, ESSCIRC ; Conference date: 16-09-1997 Through 18-09-1997",

}

Sanduleanu, MAT, Nauta, B & Wallinga, H 1997, Low-power low-voltage chopped transconductance amplifier for noise and offset reduction. in ESSCIRC '97: proceedings of the 23rd European Solid-State Circuits Conference, 1997. IEEE, Piscataway, NJ, USA, pp. 204-207, 23rd European Solid-State Circuits Conference, ESSCIRC 1997, Southampton, United Kingdom, 16/09/97. <http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1470899>

Low-power low-voltage chopped transconductance amplifier for noise and offset reduction. / Sanduleanu, M.A.T.; Nauta, Bram; Wallinga, Hans.
ESSCIRC '97: proceedings of the 23rd European Solid-State Circuits Conference, 1997. Piscataway, NJ, USA: IEEE, 1997. p. 204-207.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

AU - Sanduleanu, M.A.T.

AU - Nauta, Bram

AU - Wallinga, Hans

N1 - Conference code: 23

PY - 1997/1/26

Y1 - 1997/1/26

N2 - This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW.

AB - This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW.

KW - METIS-112856

KW - IR-15974

M3 - Conference contribution

SP - 204

EP - 207

BT - ESSCIRC '97: proceedings of the 23rd European Solid-State Circuits Conference, 1997

PB - IEEE

CY - Piscataway, NJ, USA

T2 - 23rd European Solid-State Circuits Conference, ESSCIRC 1997

Y2 - 16 September 1997 through 18 September 1997

ER -

Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

Abstract

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Keywords

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